Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
SIGNAL QUALITY
34
4.2
AGTL+ Signal Quality Specifications
Refer to the Pentium II Processor Developer's Manual (Order Number 243341) for the specification for AGTL+.
4.2.2 AGTL+ Signal Quality Specifications
Figure 12A illustrates the AGTL+ signal quality specifications for the processor for use in verifying signal quality at the
processor core pins.
These receiver signal quality specifications do not include overdrive region, ringback threshold, edge rate, and non-
monotonicity values. The receiver signal may contain ringback and non-monotonicity as long as these events do not
occur inside the Setup and Hold Time windows. The Setup Time window is the shaded region, which is bounded by
minimum V
processor core pins.
These receiver signal quality specifications do not include overdrive region, ringback threshold, edge rate, and non-
monotonicity values. The receiver signal may contain ringback and non-monotonicity as long as these events do not
occur inside the Setup and Hold Time windows. The Setup Time window is the shaded region, which is bounded by
minimum V
IH
, maximum V
IL
, T8, and the BCLK 1.25V reference crossing point. The Hold Time window is the region
bounded by minimum V
IH
, maximum V
IL
, T9, and the BCLK 1.25V reference crossing point. Note that the receiving signal
at the receiver pin may contain non-ideal signal quality events within the T8 time, as long as these events occur outside
the V
the V
IH
/ V
IL
Setup and Hold Time window boundaries.
The following conditions apply to the processor signal quality specifications:
1.
A rising edge signal must cross above minimum V
IH
prior to the Setup Time window. A falling edge signal must cross
below maximum V
IL
prior to the Setup Time window.
2.
A rising edge signal in the next cycle must cross minimum V
IL
outside the Hold Time window. A falling edge signal in
the next cycle must cross maximum V
IH
outside the Hold Time window.
3.
A rising edge flight time uses a V
IH
crossing point. A falling edge flight time uses a V
IL
crossing point. Refer to the
Pentium III Xeon processor at 700 MHz and 900 MHz Signal Integrity Models for a complete definition of flight time.
4.
For purposes of receiver signal quality, a nominal value of V
REF
(as defined in Table 10) should be used for all
conditions. Therefore, the signal quality specifications given here already include sources of noise that will vary V
IL
and V
IH
. (e.g., V
TT
tolerance, V
REF
noise, V
REF
resistor divider tolerance, etc…).
5.
This receiver specification does not comprehend maximum overshoot/undershoot limits. Refer to the Section 4.2.3
for these specifications.
for these specifications.
6.
Intel® recommends signal ringback with as much margin as possible to the V
IH
/V
IL
levels and T8/T9 times to allow
margin for other sources of system noise.
V
IH
V
IL
T8
T8: AGTL+ Input Setup Time
T9: AGTL+ Input Hold Time
T9: AGTL+ Input Hold Time
AGTL+ Falling Edge Signal
BCLK
1.25 V BCLK VRef
T9
AGTL+ Rising Edge Signal
000914a
Figure 12A. Low to High AGTL+ Receiver Ringback Tolerance
4.2.3 AGTL+
OVERSHOOT/UNDERSHOOT
GUIDELINES
Overshoot guidelines based on magnitude and duration of an overshoot/undershoot pulse (illustrated in Figure 13) are
given in Table 23 and Table 24.
given in Table 23 and Table 24.