Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
PROCESSOR FEATURES
48
5.2.2 SCRATCH
EEPROM
Also available on the SMBus is an EEPROM that may be used for other data at the system or processor
vendor’s discretion. This device has a pull-down on the WP control pin through a 10K
vendor’s discretion. This device has a pull-down on the WP control pin through a 10K
Ω resistor, as
implemented on all previous Pentium® II Xeon™ and Pentium® III Xeon™ processors. This will allow the
OEM EEPROM to be programmed in systems with no manipulation of this signal. Once programmed, the data
in this OEM EEPROM can be write protected by asserting the active-high WP signal. The Scratch EEPROM is
a 1024 bit part.
OEM EEPROM to be programmed in systems with no manipulation of this signal. Once programmed, the data
in this OEM EEPROM can be write protected by asserting the active-high WP signal. The Scratch EEPROM is
a 1024 bit part.
5.2.3
PROCESSOR INFORMATION ROM AND SCRATCH EEPROM SUPPORTED SMBUS
TRANSACTIONS
TRANSACTIONS
Four SMBus packet types are associated with the PIROM and Scratch EEPROM. Each of these packet
transfers provides a device select address and read/write bit. The remaining parts of the transfer vary. Two of
the packets, Send Byte and Receive Byte, transfer one additional byte after the device select. The other two
packets, Write Byte and Read Byte, transfer two additional bytes after the device select. By using these four
transfer types, complete access to the EEPROMs is possible.
Send Byte loads an address into the memory device that is used for subsequent access. Send Byte does not
change the contents of the EEPROM, just the address pointer within it. See Table 32 and explanation below.
Receive Byte gets a byte of data from the memory device. It uses an address already loaded into the
EEPROM device and returns the byte at that address. Repetitive use of Receive Byte to access an address
range is possible. See Table 33 and explanation below. Write Byte transfers both an address and data byte
into the memory device. It is a stand-alone write cycle. See Table 34. Read Byte transfers an address and
gets a byte of data from the memory device. It is a stand alone read cycle. See Table 35.
Both ROMs respond to SMBus packet types Send Byte, Receive Byte, and Read Byte. The Scratch EEPROM
additionally responds to the packet type Write Byte.
The EEPROM devices perform sequential read and page write modes that are not covered by the SMBus
specification. However, by use of the four transfers described above, all transfer requirements to these
devices can be achieved.
transfers provides a device select address and read/write bit. The remaining parts of the transfer vary. Two of
the packets, Send Byte and Receive Byte, transfer one additional byte after the device select. The other two
packets, Write Byte and Read Byte, transfer two additional bytes after the device select. By using these four
transfer types, complete access to the EEPROMs is possible.
Send Byte loads an address into the memory device that is used for subsequent access. Send Byte does not
change the contents of the EEPROM, just the address pointer within it. See Table 32 and explanation below.
Receive Byte gets a byte of data from the memory device. It uses an address already loaded into the
EEPROM device and returns the byte at that address. Repetitive use of Receive Byte to access an address
range is possible. See Table 33 and explanation below. Write Byte transfers both an address and data byte
into the memory device. It is a stand-alone write cycle. See Table 34. Read Byte transfers an address and
gets a byte of data from the memory device. It is a stand alone read cycle. See Table 35.
Both ROMs respond to SMBus packet types Send Byte, Receive Byte, and Read Byte. The Scratch EEPROM
additionally responds to the packet type Write Byte.
The EEPROM devices perform sequential read and page write modes that are not covered by the SMBus
specification. However, by use of the four transfers described above, all transfer requirements to these
devices can be achieved.
NOTE: In Tables 32 - 35 below:
S indicates a start condition (SDA falling while SCK high)
P indicates a stop condition (SDA rising while SCK high)
R/W* indicates a read/write not signal (1 = read, 0 = write)
A* indicates an acknowledge* signal, (0 = acknowledge, 1 = not acknowledge).
The selected SMBus slave device drives the shaded portions, while the SMBus master device under control of
the host drives the clear portions.
the host drives the clear portions.
Table 32. Send Byte SMBus Packet
S Device
Address
R/
W*
W*
A*
Data
A*
P
1 7
bits
0
0
8 bits
0
1
Table 32 outlines the Send Byte packet, which provides an address to the device for later use. A device select
field and a write bit, which are acknowledged by the device, follow the start condition. The following data byte
is really an address, which is also acknowledged by the device. Finally the stop condition is signaled.