Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
INTEGRATION TOOLS
82
NOTE
The buffer rise and fall edge rates should NOT be FASTER than 3nS. Edge rates faster than this in
the system can contribute to signal reflections that endanger ITP compatibility with the target
system. A low voltage buffer capable of driving 2.5V outputs such as an 74LVQ244 is suggested
to eliminate the need for attenuation. Simulation should be performed to verify that the edge rates
of the buffer chosen are not too fast.
the system can contribute to signal reflections that endanger ITP compatibility with the target
system. A low voltage buffer capable of driving 2.5V outputs such as an 74LVQ244 is suggested
to eliminate the need for attenuation. Simulation should be performed to verify that the edge rates
of the buffer chosen are not too fast.
The pull-up resistor to 2.5V keeps the TCK signal from floating when the ITP is not connected. The value of
this resistor should be such that the ITP can still drive the signal low (1K). The trace lengths from the buffer to
each of the agents should also be kept at a minimum to ensure good signal integrity.
8.1.7 Using the TAP to Communicate to the processor
An ITP communicates to the processor by stopping their execution and sending/receiving messages over
boundary scan pins. As long as each processor is tied into the system boundary scan chain, the ITP can
communicate with it. In the simplest case, the processors are back to back in the scan chain, with the
boundary scan input (TDI) of the first processor connected up directly to the pin labeled TDI on the debug port
and the boundary scan output of the last processor connected up to the pin labeled TDO on the debug port as
shown in Figure 32.
boundary scan pins. As long as each processor is tied into the system boundary scan chain, the ITP can
communicate with it. In the simplest case, the processors are back to back in the scan chain, with the
boundary scan input (TDI) of the first processor connected up directly to the pin labeled TDI on the debug port
and the boundary scan output of the last processor connected up to the pin labeled TDO on the debug port as
shown in Figure 32.
V
CCTAP
SC 330.1
Processor
TDI
TDO
SC 330.1
Processor
TDI
TDO
SC 330.1
Processor
TDI
TDO
SC 330.1
Processor
TDI
TDO
TDI
TDO
Debug Port
(ITP)
TDI
TDO
PCIset
Component
TDI
TDO
PCIset
Component
000799c
Note: See previous
table for recommended
pull-up resistor values.
table for recommended
pull-up resistor values.
000799c
Figure 32. System Preferred Debug Port Layout
8.2 Logic Analyzer Interconnect (LAI) and Trace Capture Tool Considerations
8.2.1 LAI and Trace Capture Tool System Design Considerations
System designers must contact their third party tools vendors for Logic Analyzer Interface design
considerations for the processor including electrical load models for system simulations. At this time, Hewlett-
Packard, Tektronix, and American Arium are currently investigating Logic Analyzer Interconnect or trace
System designers must contact their third party tools vendors for Logic Analyzer Interface design
considerations for the processor including electrical load models for system simulations. At this time, Hewlett-
Packard, Tektronix, and American Arium are currently investigating Logic Analyzer Interconnect or trace
capture tools for the processor
.
8.2.2 LAI and Trace Capture tool Mechanical Keep Outs
Please contact your third party tools vendor for mechanical keep out restrictions for the Pentium® III Xeon™
processor at 700 MHz and 900 MHz.
Please contact your third party tools vendor for mechanical keep out restrictions for the Pentium® III Xeon™
processor at 700 MHz and 900 MHz.