Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
APPENDIX
90
10. APPENDIX
This appendix provides an alphabetical listing of all Pentium® III Xeon™ processor at 700 MHz and 900 MHz signals and
tables that summarize the signals by direction: output, input, and I/O.
tables that summarize the signals by direction: output, input, and I/O.
10.1 Alphabetical Signals Reference
This section provides an alphabetical listing of all processor signals.
10.1.1 A[35:03]# (I/O)
The A[35:3]# (Address) signals define a 236-byte physical memory address space. When ADS# is active, these pins
transmit the address of a transaction; when ADS# is inactive, these pins transmit transaction type information. These
signals must connect the appropriate pins of all agents on the processor system bus. The A[35:24]# signals are parity-
protected by the AP1# parity signal, and the A[23:03]# signals are parity protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:03]# pins to determine their power-on
configuration. See the
The A[35:3]# (Address) signals define a 236-byte physical memory address space. When ADS# is active, these pins
transmit the address of a transaction; when ADS# is inactive, these pins transmit transaction type information. These
signals must connect the appropriate pins of all agents on the processor system bus. The A[35:24]# signals are parity-
protected by the AP1# parity signal, and the A[23:03]# signals are parity protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[35:03]# pins to determine their power-on
configuration. See the
Pentium II Processor Developer’s Manual
for details.
10.1.2 A20M# (I)
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit 20 (A20#) before
looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates
the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
During active RESET#, each processor begins sampling the A20M#, IGNNE#, and LINT[1:0] values to determine the ratio
of core-clock frequency to bus-clock frequency. See Figure 1. On the active-to-inactive transition of RESET#, each
processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals
for normal operation.
If the A20M# (Address-20 Mask) input signal is asserted, the processor masks physical address bit 20 (A20#) before
looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates
the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it must
be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
During active RESET#, each processor begins sampling the A20M#, IGNNE#, and LINT[1:0] values to determine the ratio
of core-clock frequency to bus-clock frequency. See Figure 1. On the active-to-inactive transition of RESET#, each
processor latches these signals and freezes the frequency ratio internally. System logic must then release these signals
for normal operation.
10.1.3 ADS# (I/O)
The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[35:03]# pins. All
bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or
deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on
all processor system bus agents.
The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction address on the A[35:03]# pins. All
bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or
deferred reply ID match operations associated with the new transaction. This signal must connect the appropriate pins on
all processor system bus agents.
10.1.4 AERR# (I/O)
The AERR# (Address Parity Error) signal is observed and driven by all processor system bus agents, and if used, must
connect the appropriate pins on all processor system bus agents. AERR# observation is optionally enabled during power-
on configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may handle an assertion of AERR# as
appropriate to the Machine Check Architecture (MCA) of the system.
The AERR# (Address Parity Error) signal is observed and driven by all processor system bus agents, and if used, must
connect the appropriate pins on all processor system bus agents. AERR# observation is optionally enabled during power-
on configuration; if enabled, a valid assertion of AERR# aborts the current transaction.
If AERR# observation is disabled during power-on configuration, a central agent may handle an assertion of AERR# as
appropriate to the Machine Check Architecture (MCA) of the system.
10.1.5 AP[1:0]# (I/O)
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:03]#, REQ[4:0]#, and RP#.
AP1# covers A[35:24]#, and AP0# covers A[23:03]#. A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals
are high. AP[1:0]# should connect the appropriate pins of all processor system bus agents.
The AP[1:0]# (Address Parity) signals are driven by the request initiator along with ADS#, A[35:03]#, REQ[4:0]#, and RP#.
AP1# covers A[35:24]#, and AP0# covers A[23:03]#. A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals
are high. AP[1:0]# should connect the appropriate pins of all processor system bus agents.
10.1.6 BCLK (I)