Intel 1.00 GHz YK80542KC0013M User Manual
Product codes
YK80542KC0013M
102
Datasheet
Signals Reference
All receiving agents observe the REQ[5:0]# signals to determine the transaction type and
participate in the transaction as necessary, as shown in
participate in the transaction as necessary, as shown in
A.1.51
RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates all caches
without writing back Modified (M state) lines. RESET# must remain asserted for one millisecond
for a “warm” reset; for a power-on reset, RESET# must stay asserted for at least one millisecond
after PWRGOOD and BCLKp have reached their proper specifications. On observing asserted
RESET#, all system bus agents must deassert their outputs within two clocks.
without writing back Modified (M state) lines. RESET# must remain asserted for one millisecond
for a “warm” reset; for a power-on reset, RESET# must stay asserted for at least one millisecond
after PWRGOOD and BCLKp have reached their proper specifications. On observing asserted
RESET#, all system bus agents must deassert their outputs within two clocks.
A number of bus signals are sampled at the asserted-to-deasserted transition of RESET# for the
power-on configuration.
power-on configuration.
Unless its outputs are tristated during power-on configuration, after asserted-to-deasserted
transition of RESET#, the processor begins program execution at the reset-vector
transition of RESET#, the processor begins program execution at the reset-vector
A.1.52
RP# (I/O)
The Request Parity (RP#) signal is driven by the requesting agent, and provides parity protection
for ADS# and REQ[5:0]#.
for ADS# and REQ[5:0]#.
Table A-10. Transaction Types Defined by REQa#/REQb# Signals
Transaction
REQa[5:0]# REQb[5:0]#
5
4
3
2
1
0
5
4
3
2
1
0
Deferred Reply
0
0
0
0
0
0
0
x
x
x
x
x
Reserved
0
0
0
0
0
1
0
x
x
x
x
x
Interrupt
Acknowledge
Acknowledge
0
0
1
0
0
0
0
DSZ[1:0]#
0
0
0
Special
Transactions
Transactions
0
0
1
0
0
0
0
DSZ[1:0]#
0
0
1
Reserved
0
0
1
0
0
0
0
DSZ[1:0]#
0
1
x
Reserved
0
0
1
0
0
1
0
DSZ[1:0]#
0
x
x
Interrupt
0
0
1
0
0
1
0
DSZ[1:0]#
1
0
0
Purge TC
0
0
1
0
0
1
0
DSZ[1:0]#
1
0
1
Reserved
0
0
1
0
0
1
0
DSZ[1:0]#
1
1
x
I/O Read
0
1
0
0
0
0
0
DSZ[1:0]#
x
x
x
I/O Write
0
1
0
0
0
1
0
DSZ[1:0]#
x
x
x
Reserved
0
1
1
0
0
x
0
DSZ[1:0]#
x
x
x
Memory Read &
Invalidate
Invalidate
0
ASZ[1:0]#
0
1
0
0
DSZ[1:0]#
LEN[2:0]#
Reserved 0
ASZ[1:0]#
0
1
1
0
DSZ[1:0]#
LEN[2:0]#
Memory Read
0
ASZ[1:0]#
1
D/C#
0
0
DSZ[1:0]#
LEN[2:0]#
Memory Read
Current
Current
1
ASZ[1:0]#
1
0
0
0
DSZ[1:0]#
LEN[2:0]#
Reserved 1
ASZ[1:0]#
1
1
0
0
DSZ[1:0]#
LEN[2:0]#
Memory Write
0
ASZ[1:0]#
1
WSNP#
1
0
DSZ[1:0]#
LEN[2:0]#
Cache Line
Replacement
Replacement
1
ASZ[1:0]#
1
WSNP#
1
0
DSZ[1:0]#
0
0
0