Intel 1.00 GHz YK80542KC0013M User Manual

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The Deferred Reply agent transmits the DID[9:0]# (Ab[25:16]#) signals received during the 
original transaction on the Aa[25:16]# signals during the Deferred Reply transaction. This process 
enables the original requesting agent to make an identifier match with the original request that is 
awaiting completion.

The Deferred Phase Enable (DPS#) signal is driven to the bus on the second clock of the Request 
Phase on the Ab[3]# pin. DPS# is asserted if a requesting agent supports transaction completion 
using the Deferred Phase. A requesting agent that supports the Deferred Phase will always assert 
DPS#. A requesting agent that does not support the Deferred Phase will always deassert DPS#.

The Data Ready (DRDY#) signal is asserted by the data driver on each data transfer, indicating 
valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert 
idle clocks.

DRDY# is replicated three times to enable partitioning of data paths in the system agents. This 
copy of the Data Ready signal (DRDY#) is an input as well as an output.

DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready signal 
(DRDY_C1#) is an output only.

DRDY# is a copy of the Data Ready signal. This copy of the Data Phase data-ready signal 
(DRDY_C2#) is an output only.

The Data Size (DSZ[1:0]#) signals are transferred on REQb[4:3]# signals in the second clock of 
the Request Phase by the requesting agent. The DSZ[1:0]# signals define the data transfer 
capability of the requesting agent. For the Itanium 2 processor, DSZ# = 01, always.

The Extended Function (EXF[4:0]#) signals are transferred on the A[7:3]# pins by the requesting 
agent during the second clock of the Request Phase. The signals specify any special functional 
requirement associated with the transaction based on the requestor mode or capability. The signals 
are defined in 

.