Intel 366 MHz 80524RX366128 Data Sheet

5

Clock Control State Machine............................................................................... 16

BCLK to Core Logic Offset ..................................................................................48

BCLK*, PICCLK, and TCK Generic Clock Waveform ......................................... 49

System Bus Valid Delay Timings ........................................................................ 49

System Bus Setup and Hold Timings.................................................................. 49

System Bus Reset and Configuration Timings (For the S.E.P. and 
PPGA Packages) ................................................................................................ 50

System Bus Reset and Configuration Timings (For the 
FC-PGA/FC-PGA2 Package) .............................................................................. 50

Power-On Reset and Configuration Timings....................................................... 51

Test Timings (TAP Connection) .......................................................................... 51

Test Reset Timings ............................................................................................. 51

BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins  .....53

BCLK, TCK, PICCLK Generic Clock Waveform at the Processor 
Edge Fingers ....................................................................................................... 54

Low to High AGTL+ Receiver Ringback Tolerance............................................. 56

Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ..................... 57

Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback  .................... 64

Processor Functional Die Layout (CPUID 0686h)............................................... 67

Processor Functional Die Layout (up to CPUID 0683h)...................................... 67

Processor Substrate Dimensions (S.E.P. Package) ........................................... 70

Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package).... 70

 Processor in the 

S.E.P. Package ................................................................................................. 111

 Celeron

®

 Processor in the PPGA Package .................................. 113

 Celeron

®

 Processor in the 

370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114