Intel III 866 MHz 80526PZ866256 User Manual
Product codes
80526PZ866256
Datasheet
39
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pins (for
2. These specifications are tested during manufacturing.
3. All timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pins (for
AGTL, the timings are referenced to the rising edge of BCLK and the falling edge of BCLK# at the processor
pins). All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V (2/3 V
pins). All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V (2/3 V
TT
for AGTL) at the
processor pins.
4. Valid delay timings for these signals are specified into 50
Ω
to 1.5 V, V
REF
at 1.0 V ±2% and with 56
Ω
on-die
R
TT
. For AGTL platforms, the valid delay timings are specified into 50
Ω
to 1.25 V, V
REF
at 2/3 V
TT
±2% and
with 56
Ω
on-die R
TT
.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. For 2-way MP
systems, RESET# should be synchronous.
7. Specification is for a minimum 0.40 V swing from V
REF
- 200 mV to V
REF
+ 200 mV. This assumes an edge
rate of 0.3V/ns.
8. Specification is for a maximum 1.0 V (2/3 V
TT
for AGTL) swing from V
TT
- 1V to V
TT
. This assumes an edge
rate of 3V/ns.
9. This should be measured after V
CCCORE
, V
TT
, Vcc
CMOS
, and BCLK become stable.
10.This specification applies to the Pentium III processor running at 100 MHz system bus frequency.
11. This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
13.For AGTL, V
11. This specification applies to the Pentium III processor running at 133 MHz system bus frequency.
12.BREQ signals at 133 MHz system bus observe a 1.2 ns minimum setup time.
13.For AGTL, V
REF
is 2/3 V
TT
±3%.
Table 16. System Bus AC Specifications (AGTL+ or AGTL Signal Group)
1, 2, 3, 13
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
0.40
3.25
ns
11
4, 10, 11
T8: AGTL+ Input Setup Time
1.20
0.95
ns
ns
12
12
5, 6, 7, 10
5, 6, 7, 11, 12
T9: AGTL+ Input Hold Time
1.00
ns
12
8, 10
T10: RESET# Pulse Width
1.00
ms
13
6, 9, 10