Intel III 866 MHz 80526PZ866256 User Manual
Product codes
80526PZ866256
Datasheet
43
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 12. System Bus Setup and Hold Timings
Figure 13. System Bus Reset and Configuration Timings
BCLK
Valid
Ts
V
Th
V
Cross
= Crossing point of BLCK and BCLK#
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups
Th = T9, T13, T28 (Hold Time)
V = Vref for AGTL signal group; 0.75V for APIC and TAP signal groups
V
Cross
BCLK#
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
Differential clock uses BCLK and BCLK#
T9 = (AGTL+ Input Hold Time)
T8 = (AGTL+ Input Setup Time)
T10 = (RESET# Pulse Width)
T16 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Setup Time)
T17 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Hold Time)
T8 = (AGTL+ Input Setup Time)
T10 = (RESET# Pulse Width)
T16 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Setup Time)
T17 = (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Hold Time)
BCLK
RESET#
Configuration
(A[14:5]#, BR0#,
BR1#, FLUSH#,
INT#)
BCLK#
Valid
T10
T16
T17
T8
T9
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
Differential clock uses BCLK and BCLK#