Intel III Xeon 500 MHz 80525KX5001M User Manual

Product codes

80525KX5001M

Datasheet

Pentium

III Xeon™ Processor at 500 and 550 MHz

Contents

Introduction.........................................................................................................................9

1.1

Terminology...........................................................................................................9
1.1.1

S.E.C. Cartridge Terminology ................................................................10

1.2

References ..........................................................................................................10

2.0

Electrical Specifications....................................................................................................11

2.1

The Pentium

III Xeon™ Processor System Bus and V

REF

...............................11

2.2

Power and Ground Pins ......................................................................................12

2.3

Decoupling Guidelines ........................................................................................12
2.3.1

Pentium

III Xeon™ Processor V

CCCORE

..............................................13

2.3.2

Level 2 Cache Decoupling .....................................................................13

2.3.3

System Bus AGTL+ Decoupling.............................................................13

2.4

System Bus Clock and Processor Clocking ........................................................13
2.4.1

Mixing Processors ..................................................................................15

2.5

Voltage Identification ...........................................................................................16

2.6

System Bus Unused Pins and Test Pins.............................................................17

2.7

System Bus Signal Groups .................................................................................18
2.7.1

Asynchronous vs. Synchronous for System Bus Signals .......................19

2.8

Test Access Port (TAP) Connection....................................................................19

2.9

Maximum Ratings................................................................................................20

2.10

Processor DC Specifications...............................................................................20

2.11

AGTL+ System Bus Specifications .....................................................................24

2.12

System Bus AC Specifications ............................................................................25

3.0

Signal Quality ...................................................................................................................32

3.1

System Bus Clock Signal Quality Specifications.................................................33

3.2

AGTL+ Signal Quality Specifications ..................................................................33
3.2.1

AGTL+ Ringback Tolerance Specifications............................................34

3.2.2

AGTL+ Overshoot/Undershoot Guidelines.............................................34

3.3

Non-AGTL+ Signal Quality Specifications...........................................................35
3.3.1

2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines .......................35

3.3.2

2.5 V Tolerant Buffer Ringback Specification.........................................35

3.3.3

2.5 V Tolerant Buffer Settling Limit Guideline ........................................36

4.0

Processor Features ..........................................................................................................36

4.1

Functional Redundancy Checking Mode.............................................................36

4.2

Low Power States and Clock Control ..................................................................37
4.2.1

Normal State— State 1 ..........................................................................37

4.2.2

Auto Halt Power Down State — State 2 .................................................37

4.2.3

Stop-Grant State — State 3 ...................................................................38

4.2.4

Halt/Grant Snoop State — State 4 .........................................................39

4.2.5

Sleep State — State 5............................................................................39

4.2.6

Clock Control..........................................................................................39

4.3

System Management Bus (SMBus) Interface .....................................................40
4.3.1

Processor Information ROM...................................................................41

4.3.2

Scratch EEPROM...................................................................................42