Intel III Xeon 500 MHz 80525KX5001M User Manual
Product codes
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
30
Datasheet
Figure 7. Setup and Hold Timings
Figure 8. FRC Mode BCLK to PICCLK Timing
Clock
Signal
V Valid
Ts
T8, T12, T27 (Setup Time)
=
Th
T9, T13, T28 (Hold Time)
=
V
2/3 V
TT
for the AGTL+ signal group; 1.25V for the CMOS, and APIC signal groups
=
T
h
T
s
Vclk
Vclk
1.25V for BCLK, and PICCLK
=
BCLK
PICCLK
1.25 V
1.25 V
Lag
Lag = T21B (FRC Mode BCLK to PICCLK offset)