Intel III Xeon 500 MHz 80525KX5001M User Manual
Product codes
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
40
Datasheet
The processor will not enter any low power states until all internal queues for the second level
cache are empty. When re-entering Normal state, the processor will resume processing external
cache requests as soon as new requests are encountered.
cache are empty. When re-entering Normal state, the processor will resume processing external
cache requests as soon as new requests are encountered.
4.3
System Management Bus (SMBus) Interface
The Pentium
III
Xeon processor includes an SMBus interface which allows access to several
processor features, including two memory components (referred to as the Processor Information
ROM and the Scratch EEPROM) and a thermal sensor on the Pentium
ROM and the Scratch EEPROM) and a thermal sensor on the Pentium
III
Xeon processor substrate.
These devices and their features are described below.
The Pentium
III
Xeon processor SMBus implementation uses the clock and data signals of the
SMBus specification. It does not implement the SMBSUS# signals.
NOTE:
Actual implementation may vary. For use in general understanding of the architecture.
Figure 17. Logical Schematic of SMBus Circuitry
V
CC_SMB
Core
Processor
Informa-
tion
ROM
SA0
A163
SA2
A159
SA1
A162
WP
B148
SMBCLK
B160
SMBDATA
B161
Thermal
Sensing
Sensing
Device
TDIODEA
TDIODEC
TDIODEC
10K
Vcc
SC
SD
A1
A0
STBY#
SC
SD
A0
A1
A2
Vcc
Scratch
EEPROM
SC
WP
SD
A0
A1
A2
Vcc
10K
10K
10K
10K
SMBALERT#
A151
ALERT#