Intel III Xeon 500 MHz 80525KX5001M User Manual
Product codes
80525KX5001M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
45
†
This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the
seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See
seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See
for details on the Thermal Sensor Device addressing.
Table 27. Write Byte SMBus Packet
S
Address
Write
Ack
Command
Ack
Data
Ack
P
1
7 bits
1
1
8 bits
1
8 bits
1
1
Table 28. Read Byte SMBus Packet
S
Addres
Write
Ack
Command
Ack
S
Addres
Read
Ack
Data
///
P
1
7 bits
1
1
8 bits
1
1
7 bits
1
1
8 bits
1
1
Table 29. Send Byte SMBus Packet
S
Addres
Write
Ack
Command
Ack
P
1
7 bits
1
1
8 bits
1
1
Table 30. Receive Byte SMBus Packet
S
Address
Read
Ack
Data
///
P
1
7 bits
1
1
8 bits
1
1
Table 31. ARA SMBus Packet
S
ARA
Read
Ack
Address
///
P
1
0001 100
1
1
Device Address
†
1
1
Table 32. Command Byte Bit Assignments (Sheet 1 of 2)
Register
Command
Reset State
Function
RESERVED
00h
N/A
Reserved for future use
RRT
01h
N/A
Read processor core thermal data
RS
02h
N/A
Read status byte (flags, busy signal)
RC
03h
0000 0000
Read configuration byte
RCR
04h
0000 0010
Read conversion rate byte
RESERVED
05h
0111 1111
Reserved for future use
RESERVED
06h
1100 1001
Reserved for future use
RRHL
07h
0111 1111
Read processor core thermal diode T
HIGH
limit
RRLL
08h
1100 1001
Read processor core thermal diode T
LOW
limit
WC
09h
N/A
Write configuration byte
WCR
0Ah
N/A
Write conversion rate byte
RESERVED
0Bh
N/A
Reserved for future use