Intel III Xeon 550 MHz 80525KY5501M User Manual
Product codes
80525KY5501M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
25
NOTES
1. The Pentium
®
III Xeon™ processor contains 1% AGTL+ termination resistors at the end of the signal trace on
the processor substrate.
2. V
REF
is generated on the processor substrate.
2.12
System Bus AC Specifications
The system bus timings specified in this section are defined at the Pentium
III
Xeon processor core
pins unless otherwise noted. Timings are tested at the processor core during manufacturing.
Timings at the processor edge fingers are specified by design characterization. Information
regarding signal characteristics between the processor core pins and the processor edge fingers is
found in the Pentium
Timings at the processor edge fingers are specified by design characterization. Information
regarding signal characteristics between the processor core pins and the processor edge fingers is
found in the Pentium
®
III
Xeon™ Processor I/O Buffer Models, Viewlogic* XTK* Format. See
for the Pentium
III
Xeon processor edge connector signal definitions.
Note:
Timing specifications T45-T49 are reserved for future use.
All system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the
BCLK input. All AGTL+ timings are referenced to 2/3 V
BCLK input. All AGTL+ timings are referenced to 2/3 V
TT
for both ‘0’ and ‘1’ logic levels unless
otherwise specified.
NOTES
1.
shows the supported ratios for each processor.
2. Minimum System Bus Frequency is not 100% tested. Specified by design characterization to allow lowe
speed system bus operation for up to 6 load systems.
3. Applies to 500MHz products.
4. Applies to 550MHz product.
5. The BCLK period allows a +0.3 ns tolerance for clock driver and routing variation. BCLK must be within
4. Applies to 550MHz product.
5. The BCLK period allows a +0.3 ns tolerance for clock driver and routing variation. BCLK must be within
specification whenever PWRGOOD is asserted.
6. It is recommended that a clock driver be used that is designed to meet the period stability specification into a
test load of 10 to 20 pF. Cycle-to-cycle jitter should be measured on adjacent rising edges of BCLK crossing
1.25 V at the processor core. This cycle-to-cycle jitter present must be accounted for as a component of flight
time between the processor(s) and/or core logic components. Positive or negative jitter of up to 150 ps is
1.25 V at the processor core. This cycle-to-cycle jitter present must be accounted for as a component of flight
time between the processor(s) and/or core logic components. Positive or negative jitter of up to 150 ps is
Table 10. Pentium
®
III Xeon™ Processor Internal Parameters for the AGTL+ Bus
Symbol
Parameter
Min
Typ
Max
Units
Notes
R
TT
Termination Resistor
150
W
1
V
REF
Bus Reference Voltage
2/3 V
TT
V
2
Table 11. System Bus AC Specifications (Clock) at the Processor Core
T#
Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
90.00
100.0
100.20
MHz
1, 2, 3
System Bus Frequency
90.00
100.00
MHz
1, 2, 4
T1:
BCLK Period
9.98
10.0
11.11
ns
3, 5
T1:
BCLK Period
10.00
11.11
ns
4, 5
T2:
BCLK Period Stability
150
ps
6, 7, 8
T3: BCLK
High
Time
2.5
ns
@>2.0 V
T4: BCLK
Low
Time
2.5
ns
@<0.5 V
T5: BCLK
Rise
Time
0.5
1.5
ns
(0.5 V–2.0 V)
9
T6: BCLK
Fall
Time
0.5
1.5
ns
(2.0 V–0.5 V)
9