Intel III Xeon 550 MHz 80525KY5501M User Manual
Product codes
80525KY5501M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
39
4.2.4
Halt/Grant Snoop State — State 4
The Pentium
III
Xeon processor will respond to snoop phase transactions (initiated by ADS#) on
the system bus while in Stop-Grant state or in Auto HALT Power Down state. When a snoop
transaction is presented upon the system bus, the processor will enter the HALT/Grant Snoop state.
The processor will stay in this state until the snoop on the system bus has been serviced (whether
by the processor or another agent on the system bus). After the snoop is serviced, the processor will
return to the Stop-Grant state or Auto HALT Power Down state, as appropriate.
transaction is presented upon the system bus, the processor will enter the HALT/Grant Snoop state.
The processor will stay in this state until the snoop on the system bus has been serviced (whether
by the processor or another agent on the system bus). After the snoop is serviced, the processor will
return to the Stop-Grant state or Auto HALT Power Down state, as appropriate.
4.2.5
Sleep State — State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains the
PLL, and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state.
Once in the Stop-Grant state (verified by the termination of the Stop-Grant Bus transaction cycle),
the SLP# pin can be asserted, causing the Pentium
PLL, and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state.
Once in the Stop-Grant state (verified by the termination of the Stop-Grant Bus transaction cycle),
the SLP# pin can be asserted, causing the Pentium
III
Xeon processor to enter the Sleep state. The
system must wait 100 BCLK cycles after the completion of the Stop-Grant Bus cycle before SLP#
is asserted. For an MP system, all processors must complete the Stop Grant bus cycle before the
subsequent 100 BCLK wait and assertion of SLP# can occur. The processor is in Sleep state 10
BCLKs after the assertion of the SLP# pin. The latency to exit the Sleep state is 10 BCLK cycles.
The SLP# pin is not recognized in the Normal, or Auto HALT States.
is asserted. For an MP system, all processors must complete the Stop Grant bus cycle before the
subsequent 100 BCLK wait and assertion of SLP# can occur. The processor is in Sleep state 10
BCLKs after the assertion of the SLP# pin. The latency to exit the Sleep state is 10 BCLK cycles.
The SLP# pin is not recognized in the Normal, or Auto HALT States.
Snoop events that occur during a transition into or out of Sleep state will cause unpredictable
behavior. Therefore, transactions should be blocked by system logic during these transitions.
behavior. Therefore, transactions should be blocked by system logic during these transitions.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals immediately after the assertion of the SLP# pin (one exception is RESET# which
causes the processor to re-initialize itself). The system core logic must detect these events and
deassert the SLP# signal (and subsequently deassert the STPCLK# signal for interrupts) for the
processor to correctly interpret any bus transaction or signal transition. Once in the Sleep state, the
SLP# pin can be deasserted if another asynchronous event occurs.
interrupt signals immediately after the assertion of the SLP# pin (one exception is RESET# which
causes the processor to re-initialize itself). The system core logic must detect these events and
deassert the SLP# signal (and subsequently deassert the STPCLK# signal for interrupts) for the
processor to correctly interpret any bus transaction or signal transition. Once in the Sleep state, the
SLP# pin can be deasserted if another asynchronous event occurs.
No transitions or assertions of signals are allowed on the system bus while the Pentium
III
Xeon
processor is in Sleep state. Any transition on an input signal (with the exception of SLP# or
RESET#) before the processor has returned to Stop Grant state will result in unpredictable
behavior.
RESET#) before the processor has returned to Stop Grant state will result in unpredictable
behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop Grant State. If RESET# is driven active while the processor is in the Sleep State and normal
operation is desired, the SLP# and STPCLK# should be deasserted immediately after RESET# is
asserted.
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop Grant State. If RESET# is driven active while the processor is in the Sleep State and normal
operation is desired, the SLP# and STPCLK# should be deasserted immediately after RESET# is
asserted.
4.2.6
Clock Control
The Pentium
III
Xeon processor provides the clock signal to the L2 Cache. The processor does not
stop this clock to the second level cache during Auto HALT Power Down or Stop-Grant states.
During Auto HALT Power Down and Stop-Grant states, the processor will continue to process the
snoop phase of a system bus cycle. The PICCLK signal should not be removed during the Auto
HALT Power Down or Stop-Grant states.
During Auto HALT Power Down and Stop-Grant states, the processor will continue to process the
snoop phase of a system bus cycle. The PICCLK signal should not be removed during the Auto
HALT Power Down or Stop-Grant states.
When the processor is in the Sleep state, it will not respond to interrupts or snoop transactions.
PICCLK can be removed during the Sleep state.
PICCLK can be removed during the Sleep state.