Intel III Xeon 550 MHz 80525KY5501M User Manual
Product codes
80525KY5501M
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
43
4.3.3
Processor Information ROM and Scratch EEPROM Supported SMBus
Transactions
Transactions
The Processor Information ROM responds to three SMBus packet types: current address read,
random address read, and sequential read. The Scratch EEPROM responds to two additional packet
types: byte write and page write.
random address read, and sequential read. The Scratch EEPROM responds to two additional packet
types: byte write and page write.
diagrams the current address read. The internal address
counter keeps track of the address accessed during the last read or write operation, incremented by
one. Address “roll over” during reads is from the last byte of the last eight byte page to the first byte
of the first page. “Roll over” during writes is from the last byte of the current eight byte page to the
first byte of the same page.
one. Address “roll over” during reads is from the last byte of the last eight byte page to the first byte
of the first page. “Roll over” during writes is from the last byte of the current eight byte page to the
first byte of the same page.
diagrams the random read. The write with no data loads the
address desired to be read.
Sequential reads may begin with a current address read or a random address read. After the SMBus
host controller receives the data word it responds with an acknowledge. This will continue until the
SMBus host controller responds with a negative acknowledge and a stop.
host controller receives the data word it responds with an acknowledge. This will continue until the
SMBus host controller responds with a negative acknowledge and a stop.
diagrams the
byte write. The page write operates the same way as the byte write except that the SMBus host
controller does not send a stop after the first data byte and acknowledge. The Scratch EEPROM
internally increments its address. The SMBus host controller continues to transmit data bytes until
it terminates the sequence with a stop. All data bytes will result in an acknowledge from the
Scratch EEPROM. If more than eight bytes are written the internal address will “roll over” and the
previous data will be overwritten. In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a
stop bit, ‘R’ represents a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge, and ‘//
/’ represents a negative acknowledge. The shaded bits are transmitted by the Processor Information
ROM or Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host
controller. In the tables the data addresses indicate 8 bits. The SMBus host controller should
transmit 8 bits, but as there are only 128 addresses, the most significant bit is a don’t care.
controller does not send a stop after the first data byte and acknowledge. The Scratch EEPROM
internally increments its address. The SMBus host controller continues to transmit data bytes until
it terminates the sequence with a stop. All data bytes will result in an acknowledge from the
Scratch EEPROM. If more than eight bytes are written the internal address will “roll over” and the
previous data will be overwritten. In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a
stop bit, ‘R’ represents a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge, and ‘//
/’ represents a negative acknowledge. The shaded bits are transmitted by the Processor Information
ROM or Scratch EEPROM, and the bits that aren’t shaded are transmitted by the SMBus host
controller. In the tables the data addresses indicate 8 bits. The SMBus host controller should
transmit 8 bits, but as there are only 128 addresses, the most significant bit is a don’t care.
4.3.4
Thermal Sensor
The Pentium
III
Xeon processor’s thermal sensor provides a means of acquiring thermal data from
the processor with an exceptional degree of precision. The thermal sensor is composed of control
logic, SMBus interface logic, a precision analog-to-digital converter, and a precision current
source. The thermal sensor drives a small current through the p-n junction of a thermal diode
located on the same silicon die as the processor core. The forward bias voltage generated across the
logic, SMBus interface logic, a precision analog-to-digital converter, and a precision current
source. The thermal sensor drives a small current through the p-n junction of a thermal diode
located on the same silicon die as the processor core. The forward bias voltage generated across the
Table 24. Current Address Read SMBus Packet
S
Device Address
R
A
Data
///
P
1
7 bits
1
1
8 bits
1
1
Table 25. Random Address Read SMBus Packet
S
Device
Address
W
A
Data
Address
A
S
Device
Address
R
A
Data
///
P
1
7 bits
1
1
8 bits
1
1
7 bits
1
1
8 bits
1
1
Table 26. Byte Write SMBus Packet
S
Device Addres
W
A
Data Addres
A
Data
A
P
1
7 bits
1
1
8 bits
1
8 bits
1
1