Intel 1.40 GHz YA80543KC0174M User Manual
Product codes
YA80543KC0174M
Datasheet
89
System Management Feature Specifications
6.7.2
Thermal Limit Registers
The thermal sensing device has two thermal limit registers; they define high and low limits for the
processor core thermal diode. The encoding for these registers is the same as for the thermal
reference registers. If the diode thermal value equals or exceeds one of its limits, then its alarm bit
in the status register is triggered. This indication is also brought out to the Itanium 2 processor
system bus via the THRMALERT# signal.
processor core thermal diode. The encoding for these registers is the same as for the thermal
reference registers. If the diode thermal value equals or exceeds one of its limits, then its alarm bit
in the status register is triggered. This indication is also brought out to the Itanium 2 processor
system bus via the THRMALERT# signal.
6.7.3
Status Register
The status register shown in
indicates which (if any) of the thermal value thresholds
have been exceeded. It also indicates if a conversion is in progress or if an open circuit has been
detected in the processor core thermal diode connection. Once set, alarm bits stay set until they are
cleared by a status register read. A successful read to the status register will clear any alarm bits
that may have been set, unless the alarm condition persists. Note that the THRMALERT# interrupt
signal is latched and is not automatically cleared when the status flag bit is cleared. The latch is
cleared by sending the Alert Response Address (0001100) on the SMBus.
detected in the processor core thermal diode connection. Once set, alarm bits stay set until they are
cleared by a status register read. A successful read to the status register will clear any alarm bits
that may have been set, unless the alarm condition persists. Note that the THRMALERT# interrupt
signal is latched and is not automatically cleared when the status flag bit is cleared. The latch is
cleared by sending the Alert Response Address (0001100) on the SMBus.
6.7.4
Configuration Register
The configuration register controls the operating mode (standby vs. auto-convert) of the thermal
sensing device.
sensing device.
shows the format of the configuration register. If the RUN/STOP bit is
set (high) then the thermal sensing device immediately stops converting and enters standby mode.
The thermal sensing device will still perform analog-to-digital conversions in standby mode when
it receives a one-shot command. If the RUN/STOP bit is clear (low) then the thermal sensor enters
auto-conversion mode. The thermal sensing device starts operating in free running mode, auto-
converting at 0.25 Hz after power-up.
The thermal sensing device will still perform analog-to-digital conversions in standby mode when
it receives a one-shot command. If the RUN/STOP bit is clear (low) then the thermal sensor enters
auto-conversion mode. The thermal sensing device starts operating in free running mode, auto-
converting at 0.25 Hz after power-up.
Table 6-14. Thermal Sensing Device Status Register
Bit
Name
Function
7 (MSB)
BUSY
A one indicates that the device’s analog to digital converter is busy converting.
6
RESERVED
Reserved for future use.
5
RESERVED
Reserved for future use.
4
RHIGH
A one indicates that the processor core thermal diode high temperature alarm has
been activated.
been activated.
3
RLOW
A one indicates that the processor core thermal diode low temperature alarm has
been activated.
been activated.
2
OPEN
A one indicates an open fault in the connection to the processor core diode.
1
RESERVED
Reserved for future use.
0 (LSB)
RESERVED
Reserved for future use.
Table 6-15. Thermal Sensing Device Configuration Register
Bit
Name
Reset
State
Function
7 (MSB)
RESERVED
0
Reserved for future use.
6
RUN/STOP
0
Standby mode control bit. If high, the device immediately stops
converting, and enters standby mode. If low, the device converts in either
one-shot or timer mode.
converting, and enters standby mode. If low, the device converts in either
one-shot or timer mode.
5–0
RESERVED
0
Reserved for future use.