Intel III 533 MHz 80526PZ533256 User Manual
Product codes
80526PZ533256
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
6
Datasheet
Tables
1
Processor Identification....................................................................................... 10
2
Voltage Identification Definition........................................................................... 21
3
System Bus Signal Groups 1 .............................................................................. 23
4
System Bus Signal Groups (AGTL)1 .................................................................. 23
5
Frequency Select Truth Table for BSEL[1:0] ...................................................... 26
6
Absolute Maximum Ratings ................................................................................ 26
7
Voltage and Current Specifications .................................................................... 28
8
PL Slew Rate Data (23A) .................................................................................... 33
9
AGTL / AGTL+ Signal Groups DC Specifications .............................................. 34
10
Non-AGTL+ Signal Group DC Specifications ..................................................... 34
11
Non-AGTL Signal Group DC Specifications ....................................................... 35
12
Processor AGTL+ Bus Specifications ................................................................ 36
13
Processor AGTL Bus Specifications .................................................................. 36
14
System Bus AC Specifications (SET Clock) ....................................................... 37
15
System Bus Timing Specifications (Differential Clock) ....................................... 38
16
System Bus AC Specifications (AGTL+ or AGTL Signal Group) ........................ 39
17
System Bus AC Specifications (CMOS Signal Group) ....................................... 40
18
System Bus AC Specifications (Reset Conditions) ............................................ 40
19
System Bus AC Specifications (APIC Clock and APIC I/O) ................................ 40
20
Platform Power-On Timings ................................................................................ 40
21
BCLK/PICCLK Signal Quality Specifications for Simulation at the
Processor Pins ................................................................................................... 46
Processor Pins ................................................................................................... 46
22
BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
in a Differential Clock Platform for AGTL ............................................................ 46
in a Differential Clock Platform for AGTL ............................................................ 46
23
AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor
Pins .................................................................................................................... 47
Pins .................................................................................................................... 47
24
Example Platform Information ............................................................................. 50
25
100 MHz AGTL+ / AGTL Signal Group Overshoot/Undershoot Tolerance at
Processor Pins .................................................................................................... 51
Processor Pins .................................................................................................... 51
26
133 MHz AGTL+/AGTL Signal Group Overshoot/Undershoot Tolerance .......... 52
27
33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at
Processor Pins .................................................................................................... 52
Processor Pins .................................................................................................... 52
28
Signal Ringback Specifications for Non-AGTL+ Signal Simulations at the
Processor Pins .................................................................................................... 55
Processor Pins .................................................................................................... 55
29
Signal Ringback Specifications for Non-AGTL Signal Simulations at
the Processor Pins ............................................................................................. 55
the Processor Pins ............................................................................................. 55
30
Intel® Pentium® III Processor Thermal Design Power for the FC-PGA Package ..
56
56
31
Intel® Pentium® III Processor for the FC-PGA2 Package Thermal
Design Power...................................................................................................... 57
Design Power...................................................................................................... 57
32
Processor Functional Die Layout for FC-PGA .................................................... 58
33
Thermal Diode Parameters ................................................................................. 59
34
Thermal Diode Interface...................................................................................... 59
35
Intel® Pentium® III Processor Package Dimensions .......................................... 61
36
Processor Die Loading Parameters for FC-PGA ................................................ 62
37
Package Dimensions for Intel® Pentium® III Processor FC-PGA2 Package ..... 63
38
Processor Case Loading Parameters for FC-PGA2 ........................................... 64
39
Signal Listing in Order by Signal Name .............................................................. 69
40
Signal Listing in Order by Pin Number ................................................................ 74