Intel III Xeon 500 MHz 80525KX500512 User Manual
Product codes
80525KX500512
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
Datasheet
15
Note:
Signal Integrity issues may require this circuit to be modified.
2.4.1
Mixing Processors
Mixing components of different internal clock frequencies is not supported and has not been
validated by Intel. Operating system support for MP with mixed frequency components should also
be considered.
validated by Intel. Operating system support for MP with mixed frequency components should also
be considered.
Also, Intel does not support or validate operation of processors with different cache sizes. Intel
only supports and validates multi-processor configurations where all processors operate with the
same system bus and core frequencies and have the same L1 and L2 cache sizes. Pentium
only supports and validates multi-processor configurations where all processors operate with the
same system bus and core frequencies and have the same L1 and L2 cache sizes. Pentium
III
Xeon
processors with different cache components, but the same cache size are validated and supported.
Similarly, Intel does not support or validate the mixing of Pentium
Similarly, Intel does not support or validate the mixing of Pentium
III
Xeon processors and Pentium
II Xeon processors in the same system bus, regardless of frequency or L2 cache sizes.
Figure 1. Timing Diagram of Clock Ratio Signals
Figure 2. Logical Schematic for Clock Ratio Pin Sharing
BCLK
RESET#
CRESET#
Ratio Pins#
Compatibility
≤
Final Ratio
Final Ratio
A20M#
IGNNE#
LINT1/NMI
LINT0/INTR
Processors
1K
Ω
2.5 V
Set Ratio:
CRESET#
Mux
2.5 V
1-4