Intel III Xeon 500 MHz 80525KX500512 User Manual
Product codes
80525KX500512
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
48
Datasheet
4.3.7
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory components claim those of the form
“1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent
addresses. The Y bit is hard-wired on the cartridge to V
“1010XXYZb”. The “XX” and “Y” bits are used to enable the devices on the cartridge at adjacent
addresses. The Y bit is hard-wired on the cartridge to V
SS
(‘0’) for the Scratch EEPROM and
pulled to V
CCSMB
US
(‘1’) for the Processor Information ROM. The “XX” bits are defined by the
processor slot via the SA0 and SA1 pins on the SC330 connector. These address pins are pulled
down weakly (10 k
down weakly (10 k
Ω
) to ensure that the memory components are in a known state in systems which
do not support the SMBus, or only support a partial implementation. The “Z” bit is the read/write
bit for the serial bus transaction.
bit for the serial bus transaction.
The thermal sensor internally decodes 1 of 3 upper address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, uses
SA2 and SA1 and includes a Hi-Z state for the SA2 address pin. Therefore the thermal sensor
supports 6 unique resulting addresses. To set the Hi-Z state for SA2, the pin must be left floating.
The system should drive SA1 and SA0, and will be pulled low (if not driven) by the 10k
“0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The device’s addressing, as implemented, uses
SA2 and SA1 and includes a Hi-Z state for the SA2 address pin. Therefore the thermal sensor
supports 6 unique resulting addresses. To set the Hi-Z state for SA2, the pin must be left floating.
The system should drive SA1 and SA0, and will be pulled low (if not driven) by the 10k
Ω
pull-
down resistor on the processor substrate. Attempting to drive either of these signals to a Hi-Z state
would cause ambiguity in the memory device address decode, possibly resulting in the devices not
responding, thus timing out or hanging the SMBus. As before, the “Z” bit is the read/write bit for
the serial bus transaction.
would cause ambiguity in the memory device address decode, possibly resulting in the devices not
responding, thus timing out or hanging the SMBus. As before, the “Z” bit is the read/write bit for
the serial bus transaction.
Note:
Addresses of the form “0000XXXXb” are Reserved and should not be generated by an SMBus
master.
master.
The thermal sensor latches the SA1 and SA2 signals at power up. System designers should ensure
that these signals are at valid input levels (see Table 9) before the thermal sensor powers up. This
should be done by pulling the pins to V
that these signals are at valid input levels (see Table 9) before the thermal sensor powers up. This
should be done by pulling the pins to V
CCSMB
US
or V
SS
via a 1 k
Ω
or smaller resistor. Additionally,
SA2 may be left unconnected to achieve the tri-state or “Z” state. If the designer desires to drive the
SA1 or SA2 pin with logic the designer must ensure that the pins are at valid input levels (see Table
9) before V
SA1 or SA2 pin with logic the designer must ensure that the pins are at valid input levels (see Table
9) before V
CCSMB
US
begins to ramp. The system designer must also ensure that their particular
system implementation does not add excessive capacitance (>50 pF) to the address inputs. Excess
capacitance at the address inputs may cause address recognition problems.
capacitance at the address inputs may cause address recognition problems.
shows a logical diagram of the pin connections.
describe the
address pin connections and how they affect the addressing of the devices.
Table 35. Thermal Sensor Conversion Rate Register
Register Contents
Conversion Rate (Hz)
00h
0.0625
01h
0.125
02h
0.25
03h
0.5
04h
1
05h
2
06h
4
07h
8
08h to FF
Reserved for future use