Intel III 450 MHz 80525PY450512 Data Sheet

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The processor will respond to snoop transactions on the Pentium III processor system bus while in 
Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor 
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the 
Pentium III processor system bus has been serviced (whether by the processor or another agent on 
the Pentium III processor system bus). After the snoop is serviced, the processor will return to the 
Stop-Grant state or AutoHALT Power Down state, as appropriate.

The Sleep state is a very low power state in which the processor maintains its context, maintains 
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be 
entered from the Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, 
causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or 
AutoHALT states.

Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will 
cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching 
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) 
are allowed on the system bus while the processor is in Sleep state. Any transition on an input 
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in 
the RESET# pin specification, then the processor will reset itself, ignoring the transition through 
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# 
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the 
processor correctly executes the Reset sequence.

While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep 
state, by stopping the BCLK input (see 

). Once in the Sleep or Deep Sleep states, the 

SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a 
minimum assertion of one BCLK period.

The Deep Sleep state is the lowest power state the processor can enter while maintaining context. 
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from 
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BCLK is 
stopped. It is recommended that the BCLK input be held low during the Deep Sleep State. Stopping 
of the BCLK input lowers the overall current consumption to leakage levels.

To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL 
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in 
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.

While in Deep Sleep state, the processor is incapable of responding to snoop transactions or 
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus 
while the processor is in Deep Sleep state. Any transition on an input signal before the processor 
has returned to Stop-Grant state will result in unpredictable behavior.