Stec UFD 4GB SLUFD4GU2TUI User Manual

Product codes
SLUFD4GU2TUI
Page of 18
SLUFDxxxU2TU(I) Data Sheet 
STEC™ Industrial Grade USB Flash Drive 
 
 
 
61000-07007-107, September 2012 
 
3.1.2  Controller External Components 
In addition to the functional blocks shown in Figure 3, the industrial grade USB flash drive has the 
following external components: 
 
SLC NAND Flash for the most reliable data storage. 
 
Crystal Oscillator 12Mhz, as the main clock source. 
3.2 
Flash Management 
Since the industrial grade USB flash drive provides a standard USB interface to the host, no software 
integration is required, providing the shortest time-to-market for design engineers. 
The firmware of the embedded USB 2.0 controller contain
s STEC‟s advanced flash memory management 
algorithms to ensure the most optimum device performance, reliability and endurance. It was designed to 
maximize the benefits of flash memory, while at the same time overcoming inherent NAND flash 
limitations. Implemented in firmware are the below features: 
 
Flash file system management  
 
Bad-block management  
 
Wear-leveling  
 
Performance optimization  
3.2.1  Bad Block Management 
Inherent to NAND flash technology are areas (blocks) on the media that cannot be used for storage 
because of their high error rate. These so-
called “bad blocks” are already identified by the flash vendor 
during manufacturing, but can also be accumulated over time during device operation.  
The USB flash memory controller contains a table that lists all the bad blocks on the device (Bad Block 
Table), and automatically maps out these blocks upon system initialization. During device operation it 
ensures that newly accumulated bad blocks are also mapped out and added to the Bad Block Table.  
Bad block management is 100% transparent to the host application, which will not be aware of the location 
or existence of bad blocks on the media. 
3.2.2  Wear Leveling 
The SLC NAND flash devices that are being used in the industrial grade USB flash drive are rated for 
100,000 Write/Erase cycles per block for 43nm flash and 60,000 Write/Erase cycles per block for 32nm 
flash. This means that after the rated erase cycles, the erase block has a higher probability for errors than 
the error rate that is typical to the flash. While standard flash write/erase cycles may be good for 
consumer data storage, such as digital cameras, MP3 players, etc., it is not sufficient for industrial and 
embedded applications where data is constantly written to the device and long product life is required.  
For example, operating systems that use a file system, will update the File Allocation Table (FAT) every 
time a write is done to the device. Without any wear leveling in place, the area on the flash where the FAT 
table is located would wear out faster than other areas, reducing the lifetime of the entire flash device.  
To overcome this limitation, the flash management algorithm needs to make sure that each block in the 
device ages, i.e. is “worn out”, at the same rate. The built-in wear leveling scheme makes sure that with 
every write to the flash, the youngest block is used. This ensures that the full flash media is used 
uniformly, so that one area of the flash will not reach the endurance limits prematurely before other areas.