Intel S2600JF BBS2600JF User Manual
Product codes
BBS2600JF
Intel®
Server Board S2600JF TPS
Product Architecture Overview
Revision 1.3
Intel order number G31608-004
15
DDR3 standard I/O Voltage of 1.5V for all speed
DDR3 Low Voltage of 1.35V for 1333MT/s or below
1Gb, 2Gb, and 4Gb DDR3 DRAM technologies supported for these devices:
DDR3 Low Voltage of 1.35V for 1333MT/s or below
1Gb, 2Gb, and 4Gb DDR3 DRAM technologies supported for these devices:
o UDIMM DDR3
– SR x8 and x16 data widths, DR – x8 data width
o RDIMM DDR3
– SR,DR, and QR – x4 and x8 data widths
o LRDIMM DDR3
– QR – x4 and x8 data widths with direct map or with
rank multiplication
Up to eight ranks supported per memory channel, 1, 2 or 4 ranks per DIMM
Open with adaptive idle page close timer or closed page policy
Per channel memory test and initialization engine can initialize DRAM to all logical zeros
Open with adaptive idle page close timer or closed page policy
Per channel memory test and initialization engine can initialize DRAM to all logical zeros
with valid ECC (with or without data scrambler) or a predefined test pattern
Isochronous access support for Quality of Service (QoS)
Minimum memory configuration: independent channel support with 1 DIMM populated
Integrated dual SMBus* master controllers
Command launch modes of 1n/2n
RAS Support:
Minimum memory configuration: independent channel support with 1 DIMM populated
Integrated dual SMBus* master controllers
Command launch modes of 1n/2n
RAS Support:
o Rank Level Sparing and Device Tagging
o Demand and Patrol Scrubbing
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
o Demand and Patrol Scrubbing
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device. Independent channel mode supports x4 SDDC. x8 SDDC requires
lockstep mode
lockstep mode
o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in
lockstep mode
o Data scrambling with address to ease detection of write errors to an
incorrect address.
o Error reporting through Machine Check Architecture
o Read Retry during CRC error handling checks by iMC
o Channel mirroring within a socket
o CPU1 Channel Mirror Pairs (A,B) and (C,D)
o CPU2 Channel Mirror Pairs (E,F) and (G,H)
o Error Containment Recovery
o Read Retry during CRC error handling checks by iMC
o Channel mirroring within a socket
o CPU1 Channel Mirror Pairs (A,B) and (C,D)
o CPU2 Channel Mirror Pairs (E,F) and (G,H)
o Error Containment Recovery
Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
Memory thermal monitoring support for DIMM temperature
Memory thermal monitoring support for DIMM temperature
3.3.2.1
Supported Memory
Color definition for the following table:
Supported and Validated
Supported but not Validate
TBD