Intel S2600JF BBS2600JF User Manual
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Product codes
BBS2600JF
Intel®
Server Board S2600JF TPS
Platform Management Functional Overview
Revision 1.3
Intel order number G31608-004
35
The Integrated BMC is provided by an embedded ARM9 controller and associated peripheral
functionality that is required for IPMI-based server management. Firmware usage of these
hardware features is platform dependent.
functionality that is required for IPMI-based server management. Firmware usage of these
hardware features is platform dependent.
The following is a summary of the Integrated BMC management hardware features that
comprise the BMC:
comprise the BMC:
400MHz 32-bit ARM9 processor with memory management unit (MMU)
Two independent10/100/1000 Ethernet Controllers with RMII/RGMII support
DDR2/3 16-bit interface with up to 800 MHz operation
12 10-bit ADCs
Sixteen fan tachometers
Eight Pulse Width Modulators (PWM)
Chassis intrusion logic
JTAG Master
Eight I
Two independent10/100/1000 Ethernet Controllers with RMII/RGMII support
DDR2/3 16-bit interface with up to 800 MHz operation
12 10-bit ADCs
Sixteen fan tachometers
Eight Pulse Width Modulators (PWM)
Chassis intrusion logic
JTAG Master
Eight I
2
C interfaces with master-slave and SMBus* timeout support. All interfaces are
SMBus 2.0* compliant.
Parallel general-purpose I/O Ports (16 direct, 32 shared)
Serial general-purpose I/O Ports (80 in and 80 out)
Three UARTs
Platform Environmental Control Interface (PECI)
Six general-purpose timers
Interrupt controller
Multiple SPI flash interfaces
NAND/Memory interface
Sixteen mailbox registers for communication between the BMC and host
LPC ROM interface
BMC watchdog timer capability
SD/MMC card controller with DMA support
LED support with programmable blink rate controls on GPIOs
Port 80h snooping capability
Secondary Service Processor (SSP), which provides the HW capability of offloading time
Serial general-purpose I/O Ports (80 in and 80 out)
Three UARTs
Platform Environmental Control Interface (PECI)
Six general-purpose timers
Interrupt controller
Multiple SPI flash interfaces
NAND/Memory interface
Sixteen mailbox registers for communication between the BMC and host
LPC ROM interface
BMC watchdog timer capability
SD/MMC card controller with DMA support
LED support with programmable blink rate controls on GPIOs
Port 80h snooping capability
Secondary Service Processor (SSP), which provides the HW capability of offloading time
critical processing tasks from the main ARM core.
Server Engines* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller
with the following features:
with the following features:
3.6.1
Super I/O Controller
The integrated super I/O controller provides support for the following features as implemented
on the server board:
on the server board:
Keyboard Style/BT interface for BMC support
Two Fully Functional Serial Ports, compatible with the 16C550
Serial IRQ Support
Two Fully Functional Serial Ports, compatible with the 16C550
Serial IRQ Support