Intel S2600JF BBS2600JF User Manual
Product codes
BBS2600JF
Intel®
Server Board S2600JF TPS
Platform Management Functional Overview
Revision 1.3
Intel order number G31608-004
43
4.4 BMC Internal Timestamp Clock
The BMC maintains an internal timestamp clock that is used by various BMC subsystems, for
example, for time stamping SEL entries. As part of BMC initialization after AC power is applied
or the BMC is reset, the BMC initializes this internal clock to the value retrieved from the SSB
component’s RTC through a SMBus* slave read operation. This is the system RTC and is on
the battery power well so it maintains the current time even when there is no AC supplied to
the system.
example, for time stamping SEL entries. As part of BMC initialization after AC power is applied
or the BMC is reset, the BMC initializes this internal clock to the value retrieved from the SSB
component’s RTC through a SMBus* slave read operation. This is the system RTC and is on
the battery power well so it maintains the current time even when there is no AC supplied to
the system.
The BMC reads the RTC using the same SMBus*
(the “host SMBus*”) that is used by BIOS
during POST, so the BMC FW must not attempt to access the RTC between the time the
system is reset or powered-on and POST completes, as indicated by the assertion of the POST-
complete signal. Additionally, the BMC should cancel any pending reads of the RTC if the
POST-complete signal de-asserts (for example, due to a reset). Normally the BMC reads the
RTC when AC power is first applied and before the system is powered-on, so this is not a
concern. However, if AC power is applied and the power button is immediately pressed, it is
possible that POST would be in progress by the time the BMC is ready to read the RTC.
Another potential conflict can occur if the BMC gets reset and POST is in progress when the
BMC has re-initialized. For either of these cases, the BMC FW initializes its internal time clock
to zero and begins counting up from there. When POST completes, BIOS will then update the
BMC
system is reset or powered-on and POST completes, as indicated by the assertion of the POST-
complete signal. Additionally, the BMC should cancel any pending reads of the RTC if the
POST-complete signal de-asserts (for example, due to a reset). Normally the BMC reads the
RTC when AC power is first applied and before the system is powered-on, so this is not a
concern. However, if AC power is applied and the power button is immediately pressed, it is
possible that POST would be in progress by the time the BMC is ready to read the RTC.
Another potential conflict can occur if the BMC gets reset and POST is in progress when the
BMC has re-initialized. For either of these cases, the BMC FW initializes its internal time clock
to zero and begins counting up from there. When POST completes, BIOS will then update the
BMC
’s time clock to the current system time.
The BMC
’s internal timestamp clock is read and set using the Get SEL Time and Set SEL Time
commands, respectively. The Get SDR Time command can also be used to read the timestamp
clock. These commands and the IPMI time format are specified in the IPMI 2.0 specification.
Whenever the BMC receives the Set SEL Time command, it updates only its internal time clock.
Note that an update of this internal time clock does not result in a change to the system RTC.
clock. These commands and the IPMI time format are specified in the IPMI 2.0 specification.
Whenever the BMC receives the Set SEL Time command, it updates only its internal time clock.
Note that an update of this internal time clock does not result in a change to the system RTC.
4.5 Sensor Monitoring
The BMC monitors system hardware and reports system health. The information gathered from
physical sensors is translated into IPMI sensors
physical sensors is translated into IPMI sensors
as part of the “IPMI Sensor Model”. The BMC
also reports various system state changes by maintaining virtual sensors that are not
specifically tied to physical hardware.
specifically tied to physical hardware.
4.6 Messaging Interfaces
The supported BMC communication interfaces include:
Host SMS interface by means of low pin count (LPC)/keyboard controller style
(KCS) interface
Host SMM interface by means of low pin count (LPC)/keyboard controller style
(KCS) interface
Intelligent Platform Management Bus (IPMB) I2C interface
LAN interface using the IPMI-over-LAN protocols
LAN interface using the IPMI-over-LAN protocols
4.6.1
Channel Management
Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. Commands are
provided to configure each channel for privilege levels and access modes. Table 16 shows the
standard channel assignments:
provided to configure each channel for privilege levels and access modes. Table 16 shows the
standard channel assignments: