IBM Intel Xeon E5-2648L 95Y4670 User Manual
Product codes
95Y4670
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
153
Datasheet Volume One
Electrical Specifications
7
Electrical Specifications
7.1
Processor Signaling
The processor includes 2011 lands, which utilize various signaling technologies. Signals
are grouped by electrical characteristics and buffer type into various signal groups.
are grouped by electrical characteristics and buffer type into various signal groups.
These include DDR3 (Reference Clock, Command, Control, and Data), PCI Express*,
DMI2, Intel QuickPath Interconnect, Platform Environmental Control Interface (PECI),
System Reference Clock, SMBus, JTAG and Test Access Port (TAP), SVID Interface,
System Reference Clock, SMBus, JTAG and Test Access Port (TAP), SVID Interface,
Processor Asynchronous Sideband, Miscellaneous, and Power/Other signals.
Refer to
for details.
Detailed layout, routing, and termination guidelines corresponding to these signal
groups can be found in the applicable platform design guide (Refer to
Intel strongly recommends performing analog simulations of all interfaces. Please refer
to
for signal integrity model availability.
7.1.1
System Memory Interface Signal Groups
The system memory interface utilizes DDR3 technology, which consists of numerous
signal groups. These include: Reference Clocks, Command Signals, Control Signals,
signal groups. These include: Reference Clocks, Command Signals, Control Signals,
and Data Signals. Each group consists of numerous signals, which may utilize various
signaling technologies. Please refer to
for further details. Throughout this
chapter the system memory interface maybe referred to as DDR3.
7.1.2
PCI Express* Signals
The PCI Express* Signal Group consists of PCI Express* ports 1, 2, and 3, and PCI
Express* miscellaneous signals. Please refer to
for further details.
7.1.3
DMI2/PCI Express* Signals
The Direct Media Interface Gen 2 (DMI2) sends and receives packets and/or commands
to the PCH. The DMI2 is an extension of the standard PCI Express* Specification. The
DMI2/PCI Express* Signals consist of DMI2 receive and transmit input/output signals
and a control signal to select DMI2 or PCIe* 2.0 operation for port 0. Please refer to
and a control signal to select DMI2 or PCIe* 2.0 operation for port 0. Please refer to
for further details.
7.1.4
Intel QuickPath Interconnect (Intel QPI)
The processor provides two Intel QPI port for high speed serial transfer between other
processors. Each port consists of two uni-directional links (for transmit and receive). A
processors. Each port consists of two uni-directional links (for transmit and receive). A
differential signaling scheme is utilized, which consists of opposite-polarity (DP, DN)
signal pairs.