IBM Intel Xeon E5-2637 49Y8125 User Manual
Product codes
49Y8125
30
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
2.5
Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is highly flexible even though underlying logic is
simple.
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is highly flexible even though underlying logic is
simple.
The interface design was optimized for interfacing to Intel processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
The PECI bus offers:
• A wide speed range from 2 Kbps to 2 Mbps
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
accuracy requirements
Note:
The PECI commands described in this document apply primarily to the Intel® Xeon®
processor E5-1600/E5-2600/E5-4600 product families. The processors utilizes the
capabilities described in this document to indicate support for four memory channels.
for the list of PECI commands supported by the processors.
2.5.1
PECI Client Capabilities
The processor PECI client is designed to support the following sideband functions:
• Processor and DRAM thermal management
• Platform manageability functions including thermal, power, and error monitoring
• Platform manageability functions including thermal, power, and error monitoring
— The platform ‘power’ management includes monitoring and control for both the
processor and DRAM subsystem to assist with data center power limiting.
• Processor interface tuning and diagnostics capabilities (Intel® Interconnect BIST).
Table 2-1.
Summary of Processor-specific PECI Commands
Command
Supported on the Processor
Ping()
Yes
GetDIB()
Yes
GetTemp()
Yes
RdPkgConfig()
Yes
WrPkgConfig()
Yes
RdIAMSR()
Yes
WrIAMSR()
No
RdPCIConfig()
Yes
WrPCIConfig()
No
RdPCIConfigLocal()
Yes
WrPCIConfigLocal()
Yes