Intel i7-3612QE AV8063801149203 User Manual

100

Datasheet, Volume 1

1.

Unless otherwise noted, all specifications in this table are based on post-silicon estimates and simulations 

or empirical data.

2.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at 

manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing 

such that two processors at the same frequency may have different settings within the VID range. This 

differs from the VID employed by the processor during a power or thermal management event (Intel 

Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).

3.

The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the 

socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum 

impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external 

noise from the system is not coupled into the oscilloscope probe.

4.

Processor core VR to be designed to electrically support this current

5.

Processor core VR to be designed to thermally support this current indefinitely.

6.

This specification assumes that Intel Turbo Boost Technology is enabled

7.

Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated.

8.

Long term reliability cannot be assured in conditions above or below Max/Min functional limits.

9.

PSx refers to the voltage regulator power state as set by the SVID protocol. 

10. Refer to Configurable TDP in 

 for TDP-Up and TDP-Down definition.

I

CC_C6/C7

I

CC

 at C6/C7 Idle-state

XE
SV-QC-45W
SV-QC-35W
SV-DC
Ultra-DC

—

—

5.5
5.0
5.0
3.0
2.5

A

10

TOL

VCC

Voltage Tolerance

PS0

—

—

±15

mV

7, 9

PS1

—

—

±12

PS2, PS3

—

—

±11.5

Ripple

Ripple Tolerance

PS0 &  

Icc > TDC+30%

—

—

±15

mV

7, 9

PS0 &  

Icc ≤ TDC+30%

—

—

±10

PS1

—

—

±13

PS2

—

—

-7.5/ +18.5

PS3

—

—

-7.5/ +27.5

VR Step

VID resolution

—

5

—

mV

SLOPE

LL

Processor Loadline

XE (TDP nom,Up,Down)
SV-QC
SV-DC
Ultra (TDP nom,Up,Down)

—

-1.9
-1.9
-1.9 
-2.9

—

mΩ