Intel i7-3920XM Extreme AW8063801009607 User Manual

Datasheet, Volume 2

147

Processor Configuration Registers 

5:2

RW

0h

Uncore

Bypass Coefficients During Phase 3 (BYPCOEFPH3) 
Bit [0]:  Controls the value of bit 7 in Symbol 6 of EQ TS1s during 

"Bypass Phase 3 Adaptation" 

1 = use preset 

0 = use coefficients 

 

The preset is defined by the per-lane DCTP field in 

EQCTL register. Coefficient values are defined within the 

appropriate EQPRESET* register, using DCTP as an 

index.

Bits [3:1]: Undefined

1

RW

0b

Uncore

Bypass Phase 3 Adaptation FSM (BYPADFSM) 
When set, when Phase 3 is entered, “bypass” coefficients will be 

sent to the link partner. When the coefficients are accepted by 

the link partner, no adaptation will be done, and Phase 3 will be 

complete.
This bit needs to be set before phase 3 start.

0

RO

0h