Intel i7-3920XM Extreme AW8063801009607 User Manual

164

Datasheet, Volume 2

8

RW

0b

Uncore

SERR# Message Enable (SERRE)
This bit controls the root port’s SERR# messaging. The processor 

communicates the SERR# condition by sending an SERR 

message to the PCH. This bit, when set, enables reporting of 

non-fatal and fatal errors detected by the device to the Root 

Complex. Note that errors are reported if enabled either through 

this bit or through the PCI Express* specific bits in the Device 

Control Register. 
In addition, for Type 1 configuration space header devices, this 

bit, when set, enables transmission by the primary interface of 

ERR_NONFATAL and ERR_FATAL error messages forwarded from 

the secondary interface. This bit does not affect the transmission 

of forwarded ERR_COR messages. 
0 = The SERR message is generated by the root port only under 

conditions enabled individually through the Device Control 

Register.

1 = The root port is enabled to generate SERR messages which 

will be sent to the PCH for specific root port error conditions 

generated/detected or received on the secondary side of the 

virtual PCI to PCI bridge. The status of SERRs generated is 

reported in the PCISTS register.

7

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0h

6

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Parity Error Response Enable (PERRE)
This bit controls whether or not the Master Data Parity Error bit in 

the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT 

be set.

1 = Master Data Parity Error bit in PCI Status register CAN be 

set.

5

RO

0b

Uncore

VGA Palette Snoop (VGAPS)
Not Applicable or Implemented. Hardwired to 0. 

4

RO

0b

Uncore

Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hardwired to 0. 

3

RO

0b

Uncore

Special Cycle Enable (SCE)
Not Applicable or Implemented. Hardwired to 0.