Intel i7-3920XM Extreme AW8063801009607 User Manual

290

Datasheet, Volume 2

This register provides the DMA address whose corresponding IOTLB entry needs to be 
invalidated through the corresponding IOTLB Invalidate register. This register is a 
write-only register.

63:39

RO

0h

38:12

RW

0000000h

Uncore

Address (ADDR) 
Software provides the DMA address that needs to be page-

selectively invalidated. To make a page-selective invalidation 

request to hardware, software must first write the appropriate 

fields in this register, and then issue the appropriate page-

selective invalidate command through the IOTLB_REG. Hardware 

ignores bits 63: N, where N is the maximum guest address width 

(MGAW) supported. 

11:7

RO

0h

6

RW

0h

Uncore

Invalidation Hint (IH) 
The field provides hint to hardware about preserving or flushing 

the non-leaf (page-directory) entries that may be cached in 

hardware:
0 = Software may have modified both leaf and non-leaf page-

table entries corresponding to mappings specified in the 

ADDR and AM fields. On a page-selective invalidation 

request, hardware must flush both the cached leaf and non-

leaf page-table entries corresponding to the mappings 

specified by ADDR and AM fields.

1 = Software has not modified any non-leaf page-table entries 

corresponding to mappings specified in the ADDR and AM 

fields. On a page-selective invalidation request, hardware 

may preserve the cached non-leaf page-table entries 

corresponding to mappings specified by ADDR and AM fields.

5:0

RW

00h

Uncore

Address Mask (AM) 
The value in this field specifies the number of low order bits of 

the ADDR field that must be masked for the invalidation 

operation. This field enables software to request invalidation of 

contiguous mappings for size-aligned regions. For example:
Mask

0

None 1

1 12 

2

2 13:12

4

3 14:12

8

4 15:12

16

When invalidating mappings for super-pages, software must 

specify the appropriate mask value. For example, when 

invalidating mapping for a 2 MB page, software must specify an 

address mask value of at least 9.
Hardware implementations report the maximum supported mask 

value through the Capability register.