Intel i7-3920XM Extreme AW8063801009607 User Manual

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Datasheet, Volume 2

DMI Interface Accesses to the processor that Cross Device Boundaries
The processor does not support transactions that cross device boundaries. This should 
never occur because PCI Express transactions are not allowed to cross a 4 KB 
boundary. For reads, the processor will provide separate completion status for each 
naturally-aligned 64 byte block or, if chaining is enabled, each 128 byte block. If the 
starting address of a transaction hits a valid address, the portion of a request that hits 
that target device (PCI Express or DRAM) will complete normally. 

If the starting transaction address hits an invalid address, the entire transaction will be 
remapped to address 000C_0000h and dispatched to DRAM. A single unsupported 
request completion will result.

1. VC0 (enabled by default)

a. Snoop port and Non-snoop Asynchronous transactions are supported.
b. Internal Graphics GMADR writes can occur. These will NOT be snooped 

regardless of the snoop not required (SNR) bit.

c. Internal Graphics GMADR reads (unsupported).
d. Peer writes can occur. The SNR bit is ignored.
e. MSI can occur. These will route and be sent to the cores as Intlogical/IntPhysical 

interrupts regardless of the SNR bit.

f.

VLW messages can occur. These will route and be sent to the cores as VLW 
messages regardless of the SNR bit.

g. MCTP messages can occur. These are routed in a peer fashion.

2. VCp (Optionally enabled)

a. Supports priority snoop traffic only. This VC is given higher priority at the snoop 

VC arbiter. Routed as an independent virtual channel and treated independently 
within the Cache module. VCp snoops are indicated as “high priority” in the 
snoop priority field. USB classic and USB2 traffic are expected to use this 
channel.  

Note: On prior chipsets, this was termed “snoop isochronous” traffic. “Snoop 
isochronous” is now termed “priority snoop” traffic.

b. SNR bit is ignored.
c. MSI on VCP is supported.
d. Peer read and write requests are not supported. Writes will route to address 

000C_0000h with byte enables deasserted, while reads will route to address 
000C_0000h and an unsupported request completion.

e. Internal Graphics GMADR writes are NOT supported. These will route to address 

000C_0000h with byte enables de-asserted.

f.

Internal Graphics GMADR reads are not supported. 

g. See DMI2 TC mapping for expected TC to VCp mapping. This has changed from 

DMI to DMI2.

3. VC1 (Optionally enabled)

a. Supports non-snoop transactions only. (Used for isochronous traffic). The PCI 

Express Egress port (PXPEPBAR) must also be programmed appropriately.

b. The snoop not required (SNR) bit must be set. Any transaction with the SNR bit 

not set will be treated as an unsupported request.

c. MSI and peer transactions will be treated as unsupported requests.
d. No “pacer” arbitration or TWRR arbitration will occur. Never remaps to a different 

port. (PCH takes care of Egress port remapping). The PCH will meter TCm Intel 
ME accesses and Intel High Definition Audio TC1 access bandwidth.