Intel i7-3920XM Extreme AW8063801009607 User Manual

Datasheet, Volume 2

91

Processor Configuration Registers 

12

RO

0b

Uncore

Received Target Abort Status (RTAS)
This bit is set when a Requester receives a Completion with 

Completer Abort Completion Status. On a Function with a Type 1 

Configuration header, the bit is set when the Completer Abort is 

received by its Primary Side.
Reset Value of this bit is 0b.
Not Applicable or Implemented. Hardwired to 0. The concept of a 

Completer abort does not exist on primary side of this device. 

11

RO

0b

Uncore

Signaled Target Abort Status (STAS)
This bit is set when a Function completes a Posted or Non-Posted 

Request as a Completer Abort error. This applies to a Function 

with a Type 1 Configuration header when the Completer Abort 

was generated by its Primary Side.
Reset Value of this bit is 0b. 
Not Applicable or Implemented. Hardwired to 0. The concept of a 

target abort does not exist on primary side of this device. 

10:9

RO

00b

Uncore

DEVSELB Timing (DEVT)
This device is not the subtractively decoded device on bus 0. This 

bit field is therefore hardwired to 00 to indicate that the device 

uses the fastest possible decode. 
Does not apply to PCI Express and must be hardwired to 00b.

8

RW1C

0b

Uncore

Master Data Parity Error (PMDPE)
This bit is set by a Requester (Primary Side for Type 1 

Configuration Space header Function) if the Party Error Response 

bit in the Command register is 1b and either of the following two 

conditions occurs:
• Requester receives a Completion marked poisoned
• Requester poisons a write Request
If the Parity Error Response bit is 0b, this bit is never set.
Reset Value of this bit is 0b.
This bit will be set only for completions of requests encountering 

ECC error in DRAM.
Poisoned peer-to-peer posted forwarded will not set this bit. They 

are reported at the receiving port. 

7

RO

0b

Uncore

Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0. 

6

RO

0h

5

RO

0b

Uncore

66/60MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0. 

4

RO

1b

Uncore

Capabilities List (CAPL)
Indicates that a capabilities list is present. Hardwired to 1. 

3

RO-V

0b

Uncore

INTx Status (INTAS)
This bit indicates that an interrupt message is pending internally 

to the device. Only PME and Hot-plug sources feed into this 

status bit (not PCI INTA–INTD assert and deassert messages). 

The INTA Assertion Disable bit, PCICMD1[10], has no effect on 

this bit. 

INTA emulation interrupts received across the link are 

not reflected in this bit. 

PCI Express* Hot-Plug is not supported on the processor. 

2:0

RO

0h