Kingston Technology Memory 1GB 800MHz DDR2 Non-ECC Low-Latency CL4 KHX6400D2LL/1G Data Sheet

Memory Module Specifications

1GB 128M x 64-Bit PC2-6400
CL4 240-Pin DIMM

Kingston.com

Document No. 4804404-001.C00    07/18/11    Page 1

This document describes Kingston’s low-latency 128M x 
64-bit 1GB (1024MB) DDR2-800 CL4 SDRAM (Synchronous 
DRAM) memory module, based on sixteen 64M x 8-bit DDR2 
FBGA components. This module has been tested to run at 
DDR2 800MHz at low latency timing of 4-4-4-12 at 2.0V. The 
SPD is programmed to JEDEC standard latency 667Mhz tim-
ing of 5-5-5-15 at 1.8V. This 240-pin DIMM uses gold contact 
fingers and requires +1.8V. The electrical and mechanical 
specifications are as follows:

Clock Cycle Time (tCK) CL=5  

3ns (min.) / 8ns (max.)

Row Cycle Time (tRC)  

54ns (min.)

Refresh to Active/Refresh  

105ns 

Command Time (tRFC)

Row Active Time (tRAS)  

39ns (min.) / 70,000ns (max.)

Single Power Supply of  

+1.8V (+/- .1V)

Power  

1.922 W (operating)

UL Rating  

94 V - 0

Operating Temperature  

0° C to 55° C

Storage Temperature  

-55° C to +125° C

•  Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
•  Double-data-rate architecture; two data transfers per  

clock cycle

•  Bidirectional data strobe(DQS)
•  Differential clock inputs(CK and CK)
•  DLL aligns DQ and DQS transition with CK transition
•  Programmable Read latency 3, 4, 5 (clock)
•  Burst Length: 4, 8 (Interleave/nibble sequential)
•  Programmable Burst type (sequential & interleave)
•  Timing Reference: 667MHz 5-5-5-15 at +1.8V / 800MHz  

4-4-4-12 at +2.0V

•  Edge aligned data output, center aligned data input
•  Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
•  Serial presence detect with EEPROM
•  High Performance Heat Spreader
•  PCB : Height 1.180” (30.00mm), double sided component

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