AMD Opteron 285 PSO-285-0026-2M Product Datasheet

Product codes
PSO-285-0026-2M
Page of 2
AMD Opteron™
Product Data Sheet
Compatible with Existing 32-Bit Code Base
Including support for SSE, SSE2, MMX™, 
3DNow!™ technology and legacy x86 instructions
Runs existing operating systems and drivers
Local APIC on-chip
AMD64 Technology
AMD64 technology instruction set extensions
64-bit integer registers, 48-bit virtual addresses, 40-
bit physical addresses
Eight new 64-bit integer registers (16 total)
Eight new 128-bit SSE/SSE2 registers (16 total)
Integrated Memory Controller
Low-latency, high-bandwidth
128-bit DDR SDRAM at 100, 133, 166, and 200 
MHz (200MHz supported by Rev C0 and later)
Supports up to eight registered DIMMs
ECC checking with double-bit detect and single-bit 
correct
HyperTransport™ Technology to I/O Devices
Three links, 16-bits in each direction, each supports 
up to 1600 MT/s or 3.2 GB/s in each direction
Each link on Uni-Processor (UP) models supports 
connections to I/O devices
Each link on Dual-Processor (DP) models supports 
connections to I/O devices, and any one of the three 
available links may connect to another DP or MP 
processor
Each link on Multi-Processor (MP) models supports 
connections to I/O devices or other DP or MP 
processors
64-Kbyte 2-Way Associative ECC-Protected 
L1 Data Cache
Two 64-bit operations per cycle, 3-cycle latency
64-Kbyte 2-Way Associative Parity-Protected 
L1 Instruction Cache
With advanced branch prediction
1024-Kbyte (1-Mbyte) 16-Way Associative 
ECC-Protected L2 Cache
Exclusive cache architecture—storage in addition 
to L1 caches
Machine Check Architecture
Includes hardware scrubbing of major ECC-
protected arrays
Power Management
Multiple low-power states
System Management Mode (SMM)
ACPI compliant
Electrical Interfaces
HyperTransport technology: LVDS-Like 
differential, unidirectional
DDR SDRAM: SSTL_2 per JEDEC specification
Clock, reset, and test signals also use DDR 
SDRAM-like electrical specifications
Packaging
940-pin lidded ceramic micro PGA
1.27-mm pin pitch
31x31 row pin array
40mm x 40mm ceramic substrate
Ceramic C4 die attach
Refer to the AMD Functional Data Sheet, 940 
Pin Package, order# 31412,
 for functional, 
electrical, and mechanical details of 940 pin 
processors
23932
Publication #
3.11
Revision:
June 2004
Issue Date: