Intel G640 CM8062307260314 User Manual
Product codes
CM8062307260314
Datasheet, Volume 1
5
Signal Description ................................................................................................... 53
6.1
6.1
Flexible Display Interface Signals ............................................................... 59
6.10 Power Sequencing ............................................................................................. 61
6.11 Processor Core Power Signals ............................................................................. 61
6.12 Graphics and Memory Core Power Signals............................................................. 63
6.13 Ground and NCTF .............................................................................................. 63
6.14 Processor Internal Pull Up/Pull Down.................................................................... 64
6.11 Processor Core Power Signals ............................................................................. 61
6.12 Graphics and Memory Core Power Signals............................................................. 63
6.13 Ground and NCTF .............................................................................................. 63
6.14 Processor Internal Pull Up/Pull Down.................................................................... 64
Electrical Specifications ........................................................................................... 65
7.1
7.1
Voltage Identification (VID) .......................................................................... 66
7.11 Platform Environmental Control Interface (PECI) DC Specifications........................... 82
7.11.1 DC Characteristics .................................................................................. 82
7.11.2 Input Device Hysteresis .......................................................................... 83
7.11.2 Input Device Hysteresis .......................................................................... 83
Processor Land and Signal Information ................................................................... 85
8.1
8.1
Figures
®
Core™ i5-600, i3-500 Desktop Processor Series and Intel
®
Pentium
®
Desktop
Processor 6000 Series Platform Diagram ..................................................................... 10
®
Flex Memory Technology Operation................................................................... 21
2-2 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes .................. 22
2-3 PCI Express* Layering Diagram ................................................................................. 24
2-4 Packet Flow through the Layers ................................................................................. 25
2-5 PCI Express Related Register Structures in the Processor .............................................. 26
2-6 Processor Graphic Processing Unit Block Diagram ......................................................... 28
2-7 Processor Display Block Diagram................................................................................ 31
4-1 Idle Power Management Breakdown of the Processor Cores ........................................... 42
4-2 Thread and Core C-State Entry and Exit ...................................................................... 42
4-3 Package C-State Entry and Exit.................................................................................. 46
7-1 V
2-3 PCI Express* Layering Diagram ................................................................................. 24
2-4 Packet Flow through the Layers ................................................................................. 25
2-5 PCI Express Related Register Structures in the Processor .............................................. 26
2-6 Processor Graphic Processing Unit Block Diagram ......................................................... 28
2-7 Processor Display Block Diagram................................................................................ 31
4-1 Idle Power Management Breakdown of the Processor Cores ........................................... 42
4-2 Thread and Core C-State Entry and Exit ...................................................................... 42
4-3 Package C-State Entry and Exit.................................................................................. 46
7-1 V
Static and Transient Tolerance Loadlines ............................................................... 77
Static and Transient Tolerance Loadlines ............................................................. 78