Intel G640T CM8062301002204 User Manual

122

Datasheet, Volume 2

This register allows control of PCI Express Root Complex specific parameters. The 
system error control bits in this register determine if corresponding SERRs are 
generated when our device detects an error (reported in this device's Device Status 
register) or when an error message is received across the link. Reporting of SERR as 
controlled by these bits takes precedence over the SERR Enable in the PCI Command 
Register.

15:4

RO

0h

3

RW

0b

Uncore

PME Interrupt Enable (PMEIE)
0 = Disable. No interrupts are generated as a result of receiving 

PME messages.

1 = Enable interrupt generation upon receipt of a PME message as 

reflected in the PME Status bit of the Root Status Register. A 

PME interrupt is also generated if the PME Status bit of the 

Root Status Register is set when this bit is set from a cleared 

state. 

If the bit changes from 1 to 0 and an interrupt is pending, the 

interrupt is de-asserted.

2

RW

0b

Uncore

System Error on Fatal Error Enable (SEFEE)
Controls the Root Complex's response to fatal errors.
0 = Disable. No SERR generated on receipt of fatal error.

1 = Enable. SERR should be generated if a fatal error is reported 

by any of the devices in the hierarchy associated with this 

Root Port, or by the Root Port itself.

1

RW

0b

Uncore

(SENFUEE)
Controls the Root Complex's response to non-fatal errors.
0 = Disable. No SERR generated on receipt of non-fatal error.

1 = Enable. SERR should be generated if a non-fatal error is 

reported by any of the devices in the hierarchy associated 

with this Root Port, or by the Root Port itself.

0

RW

0b

Uncore

System Error on Correctable Error Enable (SECEE)
Controls the Root Complex's response to correctable errors.
0 = Disable. No SERR generated on receipt of correctable error.

1 = Enable. SERR should be generated if a correctable error is 

reported by any of the devices in the hierarchy associated 

with this Root Port, or by the Root Port itself.