Intel G640T CM8062301002204 User Manual

142

Datasheet, Volume 2

A 32-bit I/O write to this port loads the offset of the MMIO register or offset into the 
GTT that needs to be accessed. An I/O Read returns the current value of this register. 

This mechanism to access internal graphics MMIO registers must not be used to access 
VGA IO registers which are mapped through the MMIO space. VGA registers must be 
accessed directly through the dedicated VGA IO ports.

A 32-bit I/O write to this port is re-directed to the MMIO register/GTT location pointed 
to by the INDEX register. A 32 bit IO read to this port is re-directed to the MMIO 
register/GTT location pointed to by the INDEX register.

0–3h

Index

MMIO Address Register

0000_0000h

RW

4–7h

Data

MMIO Data Register

0000_0000h

RW

31:21

RO

0h

20:2

RW

00000h

FLR, 

Uncore

Register/GTT Offset (REGGTTO)
This field selects any one of the DWORD registers within the MMIO 

register space of Device 2 if the target is MMIO Registers.
This field selects a GTT offset if the target is the GTT.

1:0

RW

00b

FLR, 

Uncore

Target (TARG)
00 = MMIO Registers
01 = GTT
1X = Reserved

31:0

RW

0000_000

0h

FLR, 

Uncore

MMIO Data Window (DATA)
This field is the data field associated with the IO2MMIO access.