Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
145
Processor Configuration Registers
2.10.2
DID6—Device Identification Register
This register, combined with the Vendor Identification register, uniquely identifies any
PCI device.
PCI device.
2.10.3
PCICMD6—PCI Command Register
B/D/F/Type:
0/6/0/PCI
Address Offset:
2–3h
Reset Value:
010Dh
Access:
RO-FW
Size:
16 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
15:0
RO-FW
010Dh
Uncore
Device Identification Number MSB (DID_MSB)
Identifier assigned to the processor root port (virtual PCI-to-PCI
Identifier assigned to the processor root port (virtual PCI-to-PCI
bridge, PCI Express Graphics port).
B/D/F/Type:
0/6/0/PCI
Address Offset:
4–5h
Reset Value:
0000h
Access:
RW, RO
Size:
16 bits
BIOS Optimal Default
00h
Bit
Attr
Reset
Value
RST/
PWR
Description
15:11
RO
0h
Reserved
10
RW
0b
Uncore
INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt messages.
0 = This device is permitted to generate INTA interrupt messages.
1 = This device is prevented from generating interrupt messages.
Any INTA emulation interrupts already asserted must be de-
asserted when this bit is set.
This bit only affects interrupts generated by the device (PCI INTA
from a PME or Hot Plug event) controlled by this command register.
It does not affect upstream MSIs, upstream PCI INTA–INTD assert
and deassert messages.
9
RO
0b
Uncore
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.
Not Applicable or Implemented. Hardwired to 0.
8
RW
0b
Uncore
SERR# Message Enable (SERRE)
Controls the root port SERR# messaging. The processor
Controls the root port SERR# messaging. The processor
communicates the SERR# condition by sending an SERR message
to the PCH. This bit, when set, enables reporting of non-fatal and
fatal errors detected by the device to the Root Complex. Note that
errors are reported if enabled either through this bit or through the
PCI-Express specific bits in the Device Control register.
In addition, for Type 1 configuration space header devices, this bit,
In addition, for Type 1 configuration space header devices, this bit,
when set, enables transmission by the primary interface of
ERR_NONFATAL and ERR_FATAL error messages forwarded from
the secondary interface. This bit does not affect the transmission of
forwarded ERR_COR messages.
0 = The SERR message is generated by the root port only under
0 = The SERR message is generated by the root port only under
conditions enabled individually through the Device Control
register.
1 = The root port is enabled to generate SERR messages that will
be sent to the PCH for specific root port error conditions
generated/detected or received on the secondary side of the
virtual PCI-to-PCI bridge. The status of SERRs generated is
reported in the PCISTS register.
7
RO
0h
Reserved