Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
151
Processor Configuration Registers
2.10.10 SBUSN6—Secondary Bus Number Register
This register identifies the bus number assigned to the second bus side of the "virtual"
bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
bridge (that is, to PCI Express-G). This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
2.10.11 SUBUSN6—Subordinate Bus Number Register
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
B/D/F/Type:
0/6/0/PCI
Address Offset:
19h
Reset Value:
00h
Access:
RW
Size:
8 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
7:0
RW
00h
Uncore
Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus
This field is programmed by configuration software with the bus
number assigned to PCI Express-G.
B/D/F/Type:
0/6/0/PCI
Address Offset:
1Ah
Reset Value:
00h
Access:
RW
Size:
8 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
7:0
RW
00h
Uncore
Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the
This register is programmed by configuration software with the
number of the highest subordinate bus that lies behind the
processor root port bridge. When only a single PCI device resides
on the PCI Express-G segment, this register will contain the same
value as the SBUSN1 register.