Intel G640T CM8062301002204 User Manual

Datasheet, Volume 2

165

This capability is used to uniquely identify the subsystem where the PCI device resides. 
Because this device is an integrated part of the system and not an add-in device, it is 
anticipated that this capability will never be used. However, it is necessary because 
Microsoft will test for its presence.

1:0

RW

00b

Uncore

Power State (PS)
This field indicates the current power state of this device and can be 

used to set the device into a new power state. If software attempts 

to write an unsupported state to this field, write operation must 

complete normally on the bus, but the data is discarded and no 

state change occurs.
00 = D0
01 = D1 (Not supported in this device.)
10 = D2 (Not supported in this device.)
11 = D3
Support of D3cold does not require any special action. 
While in the D3hot state, this device can only act as the target of 

PCI configuration transactions (for power management control). 

This device also cannot generate interrupts or respond to MMR 

cycles in the D3 state. The device must return to the D0 state in 

order to be fully-functional. 
When the Power State is other than D0, the bridge will Master Abort 

(that is, not claim) any downstream cycles (with exception of type 

0 configuration cycles). Consequently, these unclaimed cycles will 

go down DMI and come back up as Unsupported Requests, which 

the processor logs as Master Aborts in Device 0 PCISTS[13].
There is no additional hardware functionality required to support 

these Power States.

31:16

RO

0h

15:8

RO

80h

Uncore

Pointer to Next Capability (PNC)
This contains a pointer to the next item in the capabilities list that 

is the PCI Power Management capability.

7:0

RO

0Dh

Uncore

Capability ID (CID)
Value of 0Dh identifies this linked list item (capability structure) as 

being for SSID/SSVID registers in a PCI-to-PCI Bridge.