Intel G640T CM8062301002204 User Manual

Product codes
CM8062301002204
Page of 296
Processor Configuration Registers
20
Datasheet, Volume 2
2.3.1.3
PAM (C_0000h–F_FFFFh)
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory 
Area. Each section has Read enable and Write enable attributes. 
The PAM registers are mapped in Device 0 configuration space.
• ISA Expansion Area (C_0000h–D_FFFFh)
• Extended System BIOS Area (E_0000h–E_FFFFh)
• System BIOS Area (F_0000h–F_FFFFh)
The processor decodes the Core request, then routes to the appropriate destination 
(DRAM or DMI). 
Snooped accesses from PCI Express or DMI to this region are snooped on processor 
caches.
Non-snooped accesses from PCI Express or DMI to this region are always sent to 
DRAM. 
Graphics translated requests to this region are not allowed. If such a mapping error 
occurs, the request will be routed to C_0000h. Writes will have the byte enables de-
asserted. 
2.3.2
Main Memory Address Range (1 MB – TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that is 
permitted to be accessible by the processor (as programmed in the TOLUD register). 
The processor will route all addresses within this range to the DRAM unless it falls into 
the optional TSEG, or optional ISA Hole, or optional IGD stolen VGA memory. 
Figure 2-3. Main Memory Address Range
Main Memory
ISA Hole (optional)
DOS Compatibility Memory
0h
FLASH
FFFF_FFFFh
00F0_0000h
15 MB
16 MB
0100_0000h
0 MB
TOLUD
APIC
Main Memory
0010_0000h
1 MB
IGD
Intel TXT
PCI Memory Range
4 GB Max
Contains:
Dev 0, 1, 2, 6, 7 
BARS & PCH/PCI 
ranges
TSEG
IGGTT
DPR
TSEG_BASE