Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
225
Processor Configuration Registers
2.18.3
ECAP_REG—Extended Capability Register
This register reports remapping hardware extended capabilities.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
10–17h
Reset Value:
0000_0000_00F0_101Ah
Access:
RO, RO-V
Size:
64 bits
BIOS Optimal Default
00000000000h
Bit
Attr
Reset
Value
RST/
PWR
Description
63:24
RO
0h
Reserved
23:20
RO
1111b
Uncore
Maximum Handle Mask Value (MHMV)
The value in this field indicates the maximum supported value for
The value in this field indicates the maximum supported value for
the Handle Mask (HM) field in the interrupt entry cache invalidation
descriptor (iec_inv_dsc).
This field is valid only when the IR field in Extended Capability
This field is valid only when the IR field in Extended Capability
register is reported as set.
19:18
RO
0h
Reserved
17:8
RO
010h
Uncore
IOTLB Register Offset (IRO)
This field specifies the offset to the IOTLB registers relative to the
This field specifies the offset to the IOTLB registers relative to the
register base address of this remapping hardware unit.
If the register base address is X, and the value reported in this field
If the register base address is X, and the value reported in this field
is Y, the address for the first IOTLB invalidation register is
calculated as X+(16*Y).
7
RO
0b
Uncore
Snoop Control (SC)
0 = Hardware does not support 1-setting of the SNP field in the
0 = Hardware does not support 1-setting of the SNP field in the
page-table entries.
1 = Hardware supports the 1-setting of the SNP field in the page-
table entries.
6
RO
0b
Uncore
Pass Through (PT)
0 = Hardware does Not support pass-through translation type in
0 = Hardware does Not support pass-through translation type in
context entries.
1 = Hardware supports pass-through translation type in context
entries.
5
RO
0b
Uncore
Caching Hints (CH)
0 = Hardware does Not support IOTLB caching hints (ALH and EH
0 = Hardware does Not support IOTLB caching hints (ALH and EH
fields in context-entries are treated as reserved).
1 = Hardware supports IOTXTB caching hints through the ALH and
EH fields in context entries.
4
RO-V
1b
Uncore
Extended Interrupt Mode (EIM)
0 = On Intel 64 platforms, hardware supports only 8-bit APIC-IDs
0 = On Intel 64 platforms, hardware supports only 8-bit APIC-IDs
(xAPIC mode).
1 = On Intel 64 platforms, hardware supports 32-bit APIC-IDs
(x2APIC mode).
This field is valid only on Intel 64 platforms reporting Interrupt
Remapping support (IR field Set).
3
RO-V
1b
Uncore
Interrupt Remapping Support (IR)
0 = Hardware does Not support interrupt remapping.
0 = Hardware does Not support interrupt remapping.
1 = Hardware supports interrupt remapping.
Implementations reporting this field as set must also support
Implementations reporting this field as set must also support
Queued Invalidation (QI).
2
RO
0b
Uncore
Device IOTLB Support (DI)
0 = Hardware does not support device-IOTLBs.
0 = Hardware does not support device-IOTLBs.
1 = Hardware supports Device-IOTLBs.
Implementations reporting this field as set must also support
Implementations reporting this field as set must also support
Queued Invalidation (QI).