Intel G640T CM8062301002204 User Manual

Product codes
CM8062301002204
Page of 296
Datasheet, Volume 2
235
Processor Configuration Registers
1
ROS-V
0b
Powerg
ood
Primary Pending Fault (PPF)
This bit indicates if there are one or more pending faults logged in 
the fault recording registers. Hardware computes this bit as the 
logical OR of Fault (F) fields across all the fault recording registers 
of this remapping hardware unit.
0 = No pending faults in any of the fault recording registers
1 = One or more fault recording registers has pending faults. The 
FRI field is updated by hardware when the PPF bit is set by 
hardware. Also, depending on the programming of Fault Event 
Control register, a fault event is generated when hardware 
sets this field.
0
RW1CS
0b
Powerg
ood
Primary Fault Overflow (PFO)
Hardware sets this bit to indicate overflow of fault recording 
registers. Software writing 1 clears this bit. When this bit is set, 
hardware does not record any new faults until software clears this 
bit.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
34–37h
Reset Value:
0000_0000h
Access:
RO, ROS-V, RW1CS
Size:
32 bits
BIOS Optimal Default
00000h
Bit
Attr
Reset 
Value
RST/
PWR
Description