Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Processor Configuration Registers
244
Datasheet, Volume 2
2.18.19 IQH_REG—Invalidation Queue Head Register
This register indicates the invalidation queue head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
2.18.20 IQT_REG—Invalidation Queue Tail Register
This register indicates the invalidation tail head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
80–87h
Reset Value:
0000_0000_0000_0000h
Access:
RO-V
Size:
64 bits
BIOS Optimal Default
0_0000_0000_0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
63:19
RO
0h
Reserved
18:4
RO-V
0000h
Uncore
Queue Head (QH)
This field specifies the offset (128-bit aligned) to the invalidation
This field specifies the offset (128-bit aligned) to the invalidation
queue for the command that will be fetched next by hardware.
Hardware resets this field to 0 whenever the queued invalidation is
Hardware resets this field to 0 whenever the queued invalidation is
disabled (QIES field Clear in the Global Status register).
3:0
RO
0h
Reserved
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
88–8Fh
Reset Value:
0000_0000_0000_0000h
Access:
RW-L
Size:
64 bits
BIOS Optimal Default
0_0000_0000_0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
63:19
RO
0h
Reserved
18:4
RW-L
0000h
Uncore
Queue Tail (QT)
This field specifies the offset (128-bit aligned) to the invalidation
This field specifies the offset (128-bit aligned) to the invalidation
queue for the command that will be written next by software.
3:0
RO
0h
Reserved