Intel G640T CM8062301002204 User Manual

270

Datasheet, Volume 2

This register controls remapping hardware. If multiple control fields in this register 
need to be modified, software must serialize the modifications through multiple writes 
to this register.

1

RO-V

1b

Uncore

Queued Invalidation Support (QI)
0 = Hardware does not support queued invalidations.

1 = Hardware supports queued invalidations. 

0

RO

0b

Uncore

Coherency (C)
This field indicates if hardware access to the root, context, page-

table and interrupt-remap structures are coherent (snooped) or 

not.
0 = Indicates hardware accesses to remapping structures are non-

coherent.

1 = Indicates hardware accesses to remapping structures are 

coherent.

Hardware access to advanced fault log and invalidation queue are 

always coherent.

31

WO

0b

Uncore

Translation Enable (TE)
Software writes to this field to request hardware to enable/disable 

DMA-remapping:
0 = Disable DMA remapping

1 = Enable DMA remapping
Hardware reports the status of the translation enable operation 

through the TES field in the Global Status register.
There may be active DMA requests in the platform when software 

updates this field. Hardware must enable or disable remapping 

logic only at deterministic transaction boundaries, so that any in-

flight transaction is either subject to remapping or not at all.
Hardware implementations supporting DMA draining must drain 

any in-flight DMA read/write requests queued within the Root-

Complex before completing the translation enable command and 

reflecting the status of the command through the TES field in the 

Global Status register.
The value returned on a read of this field is undefined.