Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
275
Processor Configuration Registers
2.21.6
RTADDR_REG—Root-Entry Table Address Register
This register provides the base address of root-entry table.
23
RO-V
0b
Uncore
Compatibility Format Interrupt Status (CFIS)
This field indicates the status of Compatibility format interrupts on
This field indicates the status of Compatibility format interrupts on
Intel 64 implementations supporting interrupt-remapping. The
value reported in this field is applicable only when interrupt-
remapping is enabled and Extended Interrupt Mode (x2APIC mode)
is not enabled.
0 = Compatibility format interrupts are blocked.
0 = Compatibility format interrupts are blocked.
1 = Compatibility format interrupts are processed as pass-through
(bypassing interrupt remapping).
22:0
RO
0h
Reserved
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
1C–1Fh
Reset Value:
0000_0000h
Access:
RO, RO-V
Size:
32 bits
BIOS Optimal Default
00_0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
20–27h
Reset Value:
0000_0000_0000_0000h
Access:
RW
Size:
64 bits
BIOS Optimal Default
00_0000_0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
63:39
RO
0h
Reserved
38:12
RW
0000000h
Uncore
Root Table Address (RTA)
This register points to base of page aligned, 4 KB-sized root-entry
This register points to base of page aligned, 4 KB-sized root-entry
table in system memory. Hardware ignores and not implements
bits 63:HAW, where HAW is the host address width.
Software specifies the base address of the root-entry table through
Software specifies the base address of the root-entry table through
this register, and programs it in hardware through the SRTP field in
the Global Command register.
Reads of this register returns value that was last programmed to it.
Reads of this register returns value that was last programmed to it.
11:0
RO
0h
Reserved