Intel G640T CM8062301002204 User Manual

Datasheet, Volume 2

283

This register enables the DMA-protected memory regions setup through the PLMBASE, 
PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for 
implementations not supporting protected memory regions (PLMR and PHMR fields 
reported as Clear in the Capability register).

Protected memory regions may be used by software to securely initialize remapping 
structures in memory. To avoid impact to legacy BIOS usage of memory, software is 
recommended to not overlap protected memory regions with any reserved memory 
regions of the platform reported through the Reserved Memory Region Reporting 
(RMRR) structures.

31

RW

0h

Uncore

Enable Protected Memory (EPM)
This field controls DMA accesses to the protected low-memory and 

protected high-memory regions.
0 = Protected memory regions are disabled.

1 = Protected memory regions are enabled. DMA requests 

accessing protected memory regions are handled as follows:

— When DMA remapping is not enabled, all DMA requests 

accessing protected memory regions are blocked.

— When DMA remapping is enabled:

—

DMA requests processed as pass-through 

(Translation Type value of 10b in Context-Entry) 

and accessing the protected memory regions are 

blocked.

—

DMA requests with translated address (AT=10b) 

and accessing the protected memory regions are 

blocked.

—

DMA requests that are subject to address 

remapping, and accessing the protected memory 

regions may or may not be blocked by hardware. 

For such requests, software must not depend on 

hardware protection of the protected memory 

regions, and instead program the DMA-remapping 

page-tables to not allow DMA to protected memory 

regions.

Remapping hardware access to the remapping structures are not 

subject to protected memory region checks.
DMA requests blocked due to protected memory region violation 

are not recorded or reported as remapping faults.
Hardware reports the status of the protected memory 

enable/disable operation through the PRS field in this register. 

Hardware implementations supporting DMA draining must drain 

any in-flight translated DMA requests queued within the Root-

Complex before indicating the protected memory region as enabled 

through the PRS field. 

30:1

RO

0h

0

RO-V

0h

Uncore

Protected Region Status (PRS)
This field indicates the status of protected memory region(s).
0 = Protected memory region(s) disabled.

1 = Protected memory region(s) enabled.