Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Processor Configuration Registers
32
Datasheet, Volume 2
Implementation Notes
• Remap applies to transactions from all interfaces. All upstream PEG/DMI
transactions that are snooped get remapped.
• Upstream PEG/DMI transactions that are not snooped (“Snoop not required”
attribute set) get remapped.
• Upstream reads and writes above TOUUD are treated as invalid cycles.
• Remapped addresses remap starting at TOLUD. They do not remap starting at
• Remapped addresses remap starting at TOLUD. They do not remap starting at
TSEG_BASE. DMI and PEG need to be careful with this for both snoop and non-
snoop accesses. In other words, for upstream accesses, the range between
(TOLUD – GfxStolensize-GFXGTTstolensize – TSEGSIZE-DPR) to TOLUD) will never
map directly to memory.
snoop accesses. In other words, for upstream accesses, the range between
(TOLUD – GfxStolensize-GFXGTTstolensize – TSEGSIZE-DPR) to TOLUD) will never
map directly to memory.
Note:
Accesses from PEG/DMI should be decoded as to the type of access before they are
remapped. For instance a DMI write to FEEx_xxxx is an interrupt transaction, but there
is a DMI address that will be re-mapped to the DRAM address of FEEx_xxxx. In all
cases, the remapping of the address is done only after all other decodes have taken
place.
Unmapped Addresses between TOLUD and 4 GB
Accesses that do not hit DRAM or PCI space are subtractive decoded to DMI. Because
the TOLUD register is used to mark the upper limit of DRAM space below the 4 GB
boundary, no address between TOLUD and 4 GB ever decodes directly to main memory.
Thus, even if remap is disabled, any address in this range has a non-memory
destination.
the TOLUD register is used to mark the upper limit of DRAM space below the 4 GB
boundary, no address between TOLUD and 4 GB ever decodes directly to main memory.
Thus, even if remap is disabled, any address in this range has a non-memory
destination.
The top of DRAM address space is either:
• TOLUD if there is less then 4 GB of DRAM or 32-bit addressing or
• TOUUD if there is more than 4 GB of DRAM and 36-bit addressing.
• TOUUD if there is more than 4 GB of DRAM and 36-bit addressing.
Note:
The system address space includes the remapped range. For instance, if there is 8 GB
of DRAM and 1 GB of PCI space, the system has a 9 GB address space, where DRAM
lies from 0-3 GB and 4-9 GB. BIOS will report an address space of 9 GB to the OS.
2.3.5
PCI Express* Configuration Address Space
Unlike previous platforms, PCIEXBAR is located in device 0 configuration space as in
FSB platforms. The processor detects memory accesses targeting PCIEXBAR. BIOS
must assign this address range such that it will not conflict with any other address
ranges.
FSB platforms. The processor detects memory accesses targeting PCIEXBAR. BIOS
must assign this address range such that it will not conflict with any other address
ranges.
See the configuration portion of this document for more details.