Intel G640T CM8062301002204 User Manual
Product codes
CM8062301002204
Datasheet, Volume 2
81
Processor Configuration Registers
2.5.33
CAPID0_A—Capabilities A Register
This register control of bits in this register are only required for customer visible SKU
differentiation.
B/D/F/Type:
0/0/0/PCI
Address Offset:
E4–E7h
Default Value:
0000_0000h
Access:
RO-FW, RO-KFW
Size:
32 bits
BIOS Optimal Default:
000000h
Bit
Attr
Reset
Value
RST/
PWR
Description
31
RO-KFW
0b
Reserved
30
RO-KFW
0b
Reserved
29
RO-KFW
0b
Reserved
28
RO-KFW
0b
Reserved
27
RO-FW
0b
Reserved
26
RO-FW
0b
Reserved
25
RO-FW
0b
Reserved
24
RO-FW
0b
Reserved
23
RO-KFW
0b
Uncore
VT-d Disable (VTDD)
0 = Enable VT-d
0 = Enable VT-d
1 = Disable VT-d
22
RO-FW
0b
Reserved
21
RO-FW
0b
Reserved
20:19
RO-FW
00b
Reserved
18
RO-FW
0b
Reserved
17
RO-FW
0b
Reserved
16
RO-FW
0b
Reserved
15
RO-KFW
0b
Reserved
14
RO-FW
0b
Uncore
2 DIMMS per Channel Disable (DDPCD)
Allows Dual Channel operation but only supports 1 DIMM per
Allows Dual Channel operation but only supports 1 DIMM per
channel.
0 = 2 DIMMs per channel enabled
0 = 2 DIMMs per channel enabled
1 = 2 DIMMs per channel disabled. This setting hardwires bits
2 and 3 of the rank population field for each channel to
zero. (MCHBAR offset 260h, bits 22–23 for channel 0 and
MCHBAR offset 660h, bits 22–23 for channel 1)
13
RO-FW
0b
Reserved
12
RO-FW
0b
Reserved
11
RO-KFW
0b
Reserved
10
RO-FW
0b
Reserved
9:8
RO-FW
00b
Reserved